Texas Instruments TNETX4090 Jtag Instruction Opcodes, Highz instruction, Racbist instruction

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

JTAG interface

The TNETX4090 is fully IEEE Std 1149.1 compliant. It also includes on-chip pullup resistors on the five JTAG terminals to eliminate the need for external ones. The instructions that TI supports are:

DMandatory (EXTEST, BYPASS, and SAMPLE/PRELOAD)

DOptional public (HIGHZ, IDCODE, and BIST)

DPrivate (various private instructions are used by TI for test purposes)

The opcodes for the various instructions (6-bit instruction register) are shown in Table 18.

Table 18. JTAG Instruction Opcodes

INSTRUCTION	INSTRUCTION	JTAG
TYPE	NAME	OPCODE
Mandatory	EXTEST	000000
Mandatory	SAMPLE/PRELOAD	000001
Optional	IDCODE	000100
Optional	HIGHZ	000101
Optional	RACBIST	000110
Private	TI testing	Others
Mandatory	BYPASS	111111

HIGHZ instruction

When selected, the HIGHZ instruction causes all outputs and bidirectional terminals to become high impedance. All pullup and pulldown resistors are disabled.

RACBIST instruction

The RACBIST instruction invokes a built-in self test of the RAC and the rambus channel. This tests the integrity of the connection between the TNETX4090 and the external RDRAMs. When selected, the value of the test can be read via JTAG DR SCAN. A 2-bit status value is reported (see Table 19).

Table 19. JTAG BIST Status

PASS		COMPLETE
(BIT 1)		(BIT 0)
When bit 0 = 1		*0 = BIST running
*0	= fail
		*1 = BIST complete
*1	= pass

The IDCODE for the TNETX4090 is shown in Table 20.

Table 20. JTAG ID Code

VARIANT		PART NUMBER		MANUFACTURE		LEAST SIGNIFICANT BIT
BIT 31	BIT 28	BIT 27	BIT 12	BIT 11	BIT 1	BIT 0
0000		1011000111110111		00000010111		1

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