Jtag Instruction Opcodes | Texas Instruments TNETX4090 specification

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

JTAG interface

The TNETX4090 is fully IEEE Std 1149.1 compliant. It also includes on-chip pullup resistors on the five JTAG terminals to eliminate the need for external ones. The instructions that TI supports are:

DMandatory (EXTEST, BYPASS, and SAMPLE/PRELOAD)

DOptional public (HIGHZ, IDCODE, and BIST)

DPrivate (various private instructions are used by TI for test purposes)

The opcodes for the various instructions (6-bit instruction register) are shown in Table 18.

Table 18. JTAG Instruction Opcodes

INSTRUCTION	INSTRUCTION	JTAG
TYPE	NAME	OPCODE

Mandatory	EXTEST	000000

Mandatory	SAMPLE/PRELOAD	000001

Optional	IDCODE	000100

Optional	HIGHZ	000101

Optional	RACBIST	000110

Private	TI testing	Others

Mandatory	BYPASS	111111

HIGHZ instruction

When selected, the HIGHZ instruction causes all outputs and bidirectional terminals to become high impedance. All pullup and pulldown resistors are disabled.

RACBIST instruction

The RACBIST instruction invokes a built-in self test of the RAC and the rambus channel. This tests the integrity of the connection between the TNETX4090 and the external RDRAMs. When selected, the value of the test can be read via JTAG DR SCAN. A 2-bit status value is reported (see Table 19).

Table 19. JTAG BIST Status

	PASS		COMPLETE
	(BIT 1)		(BIT 0)

	When bit 0 = 1		*0 = BIST running
	*0	= fail
	*0	= fail	*1 = BIST complete
	*1	= pass	*1 = BIST complete

The IDCODE for the TNETX4090 is shown in Table 20.

Table 20. JTAG ID Code

VARIANT		PART NUMBER		MANUFACTURE		LEAST SIGNIFICANT BIT

BIT 31	BIT 28	BIT 27	BIT 12	BIT 11	BIT 1	BIT 0

0000		1011000111110111		00000010111		1

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

47

Image 47

Texas Instruments TNETX4090 Jtag Instruction Opcodes, Highz instruction, Racbist instruction, Jtag Bist Status

Contents

Description DMA MIIMAC MII MAC Eeprom CPU I/F PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted Alphabetically Reset Sdma SAD0 Terminal Internal Description Name RESISTOR² Terminal FunctionsJtag interface Control logic interface M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii mode Terminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7 M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch MII management interface Rdram interface Eeprom interface DIO interface 100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail 0x90Ex Port no Head Statistic Tail Receiving/transmitting management frames DMA Interface SignalsSignal Description Address-Lookup Statistics Ieee Std 802.1Q Vlan tags on the NM port State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset DIO Interface State During Hardware Reset CRC Vlan IDFCS Tpid TCI TNETX4090 Interrupt processing PHY management interfaceFull-duplex NM port NM bandwidth and priority MAC interface Receive versus transmit priority Adaptive performance optimization APOInterframe gap enforcement Backoff Speed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Outcome Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Full-duplex hardware flow control M08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission BIT Name Function Transmit Pretag Bit DefinitionsPretag on reception Learning Format Receive Pretag Bit Definitions TNETX4090 RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology RXD Flow COL TXD M08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register State Display Compatibility with future device revisionsPort LED States Collision LED States Multi-LED display PCS duplex LEDLED Status Bit Definitions and Shift Order Lamp test Sout SCHAIN0 Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN TNETX4090 VCC NC Txclk Vref Rxclk VDD Jtag Bist Status Jtag Instruction OpcodesHighz instruction Racbist instruction Iale Frame routingVlan support Spanning-tree support Address maintenanceIeee Std 802.1Q tags ± reception Ieee Std 802.1Q header ± transmission Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharing Extended port awareness Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Trunk Group 1 Port Membership Trunk1Ports Register Flow control System test capabilities Other flow-control mechanismsHardware flow control Multicast limit Internal wrap test Reading Rdram PHY TNETX4090 Duplex wrap test MIN NOM MAX Unit Recommended operating conditions Timing requirements over recommended operating conditions Jtag interface Control signalsReset see Figure PMA receive see Figure Physical medium attachment interface port Receive PMA transmit see Figure Transmit Gmii transmit see Figure Gmii portGmii receive see Figure Gmii Clock PMA and Gmii clock see Figure MII receive see Figure MII ports 0±8 MII clock see Figure MII transmit see Figure Dbusctrl Dbusen Rdram interfaceRdram see Figure Dtxclk Drxclk SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see Figure Eeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOL VOH TTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TBD TNETX4090GGP Obsolete BGA Important Notice