Ring-Topology Connectivity | Texas Instruments TNETX4090 instruction

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

ring-cascade topology (continued)

DFrames received on a ring port must have an out-of-band pretag in the clock cycle before Mxx_RXDV is asserted. The contents of the pretag are examined, and based on the results, are either forwarded normally, or immediately discarded within the MAC. If discarded, the frame does not affect any of the statistics or address-lookup database. Frames are forwarded normally, unless:

±The pretag is 0.

±The two IDs within the pretag are not the same.

±The ID within the received pretag is the same as ringid. This identifies a frame that originated at this device, and that has passed completely around the ring.

The pretag format is shown in Figure 8.

M08_GTCLK

M08_TXEN

M08_RXDV

	M08_TXD3±
	M08_TXD0/	Ring ID	Preamble
	M08_RXD3±	Ring ID	Preamble
	M08_RXD3±
	M08_RXD0
	M08_TXD7±
	M08_TXD4/	Ring ID	Preamble
	M08_RXD7±
	M08_RXD4

Figure 8. Ring-Topology Pretag Timing

The devices in the ring are connected as shown in Table 13.

Table 13. Ring-Topology Connectivity

SWITCH TERMINAL

n		n + 1

M08_TXD7	→	M08_RXD7

M08_TXD6	→	M08_RXD6

M08_TXD5	→	M08_RXD5

M08_TXD4	→	M08_RXD4

M08_TXD3	→	M08_RXD3

M08_TXD2	→	M08_RXD2

M08_TXD1	→	M08_RXD1

M08_TXD0	→	M08_RXD0

M08_TXEN	→	M08_RXDV

M08_TXER	→	M08_RXER

M08_COL	←	FLOW

NOTE: When a port is configured for the ring topology, IEEE Std 802.3x flow control should be disabled. Hardware-based flow control is supported using the FLOW and Mxx_COL terminals; however, this must be enabled by setting the flow bit in SysControl.

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Texas Instruments TNETX4090 specifications Ring-Topology Connectivity, M08GTCLK M08TXEN M08RXDV, Switch Terminal

Contents

Description MAC MII MIIMAC Eeprom CPU I/F DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted Alphabetically Reset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR² M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii mode Terminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7 M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch MII management interface Rdram interface Eeprom interface DIO interface 100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail 0x90Ex Port no Head Statistic Tail Signal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management frames DIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port FCS Vlan IDTpid TCI CRC TNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processing MAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit priority Speed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control Outcome M08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name Function Ring-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXD M08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Port LED States Compatibility with future device revisionsCollision LED States State Display LED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED display BUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDD Highz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist Status Iale Frame routingVlan support Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharing Trunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awareness Flow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilities Internal wrap test Reading Rdram PHY TNETX4090 Duplex wrap test MIN NOM MAX Unit Recommended operating conditions Timing requirements over recommended operating conditions Jtag interface Control signalsReset see Figure PMA receive see Figure Physical medium attachment interface port Receive PMA transmit see Figure Transmit Gmii transmit see Figure Gmii portGmii receive see Figure Gmii Clock PMA and Gmii clock see Figure MII receive see Figure MII ports 0±8 MII clock see Figure MII transmit see Figure Rdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl Dbusen SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see Figure Eeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOL VOH TTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TBD TNETX4090GGP Obsolete BGA Important Notice