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Texas Instruments TNETX4090 DIO interface description, DIO Internal Register Address Map

Models: TNETX4090

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TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

DIO interface description

The DIO is a general-purpose interface that is used with a range of microprocessor or computer system interfaces. The interface is backward compatible with the existing TI ThunderSWITCH products. The DIO provides new signals to support external DMA controllers for improved performance.

This interface configures the switch using the attached CPU, and to access statistics registers (see Table 2). DIO accesses the NM port to allow frame data to be transferred between the CPU and the switch to support spanning tree, SNMP, and RMON. The CPU reads and writes packets directly under software control or an external DMA controller can be used to improve performance. See TNETX4090 Programmer's Reference Guide, literature number SPAU003, for description of registers.

Table 2. DIO Internal Register Address Map

BYTE 3		BYTE 2		BYTE 1		BYTE 0	DIO
BYTE 3		BYTE 2		BYTE 1		BYTE 0	ADDRESS
							ADDRESS

	Port1Control				Port0Control		0x0000

	Port3Control				Port2Control		0x0004

	Port5Control				Port4Control		0x0008

	Port7Control				Port6Control		0x000C

	Reserved				Port8Control		0x0010

			Reserved				0x0014±0x003C

Reserved		UnkVLANPort		MirrorPort		UplinkPort	0x0040

	Reserved			AgingThreshold			0x0044

			Reserved				0x0048±0x004C

			NLearnPorts				0x0050

			TxBlockPorts				0x0054

		RxUniBlockPorts					0x0058

		RxMultiBlockPorts					0x005C

			UnkUniPorts				0x0060

			UnkMultiPorts				0x0064

			UnkSrcPorts				0x0068

		NewVLANIntPorts					0x006C

			Reserved				0x0070±0x007C

TrunkMap3		TrunkMap2		TrunkMap1		TrunkMap0	0x0080

TrunkMap7		TrunkMap6		TrunkMap5		TrunkMap4	0x0084

Trunk3Ports		Trunk2Ports		Trunk1Ports		Trunk0Ports	0x0088

		Reserved				RingPorts	0x008C

			Reserved				0x0090±0x009C

DevCode		Reserved		SIO		Revision	0x00A0

DevNode[23:16]		DevNode[31:24]		DevNode[39:32]		DevNode[47:40]	0x00A4

	Reserved			DevNode[7:0]		DevNode[15:8]	0x00A8

			MCastLimit				0x00DC

RamStatus		RamControl			Reserved		0x00E0

			Reserved				0x00E4

PauseTime100					PauseTime10		0x00E8

PauseTime1000					Reserved		0x00EC

Reserved				FlowThreshold			0x00F0

	Reserved				LEDControl		0x00F4

18	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Texas Instruments TNETX4090 specifications DIO interface description, DIO Internal Register Address Map, Byte DIO Address

Contents

Description MAC Eeprom CPU I/F MIIMAC MII DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball NameReset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR²100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 PulldownM00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4MII management interface Rdram interface DIO interface Eeprom interfacePower supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90ExAddress-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management framesDIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portTpid TCI Vlan IDFCS CRCTNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processingMAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode OutcomePretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name FunctionRXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXDSwitch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Collision LED States Compatibility with future device revisionsPort LED States State DisplayLamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED displayTNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDDRacbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist StatusFrame routing Vlan supportIale Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source portTrunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awarenessFlow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilitiesReading Rdram Internal wrap testDuplex wrap test PHY TNETX4090Recommended operating conditions MIN NOM MAX UnitJtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see FigureTransmit PMA transmit see FigureGmii port Gmii receive see FigureGmii transmit see Figure PMA and Gmii clock see Figure Gmii ClockMII ports 0±8 MII receive see FigureMII transmit see Figure MII clock see FigureDtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl DbusenDIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 SrdyEeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOH VOLTTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBDImportant Notice