VLAN1QID VLAN0QID | Texas Instruments TNETX4090 manual

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

Table 2. DIO Internal Register Address Map (Continued)

BYTE 3		BYTE 2		BYTE 1			BYTE 0	DIO
BYTE 3		BYTE 2		BYTE 1			BYTE 0	ADDRESS
								ADDRESS

			VLAN40Ports					0x01A0

			VLAN41Ports					0x01A4

			VLAN42Ports					0x01A8

			VLAN43Ports					0x01AC

			VLAN44Ports					0x01B0

			VLAN45Ports					0x01B4

			VLAN46Ports					0x01B8

			VLAN47Ports					0x01BC

			VLAN48Ports					0x01C0

			VLAN49Ports					0x01C4

			VLAN50Ports					0x01C8

			VLAN51Ports					0x01CC

			VLAN52Ports					0x01D0

			VLAN53Ports					0x01D4

			VLAN54Ports					0x01D8

			VLAN55Ports					0x01DC

			VLAN56Ports					0x01E0

			VLAN57Ports					0x01E4

			VLAN58Ports					0x01E8

			VLAN59Ports					0x01EC

			VLAN60Ports					0x01F0

			VLAN61Ports					0x01F4

			VLAN62Ports					0x01F8

			VLAN63Ports					0x01FC

			Reserved					0x0200±0x02FC

	VLAN1QID				VLAN0QID			0x0300

	VLAN3QID				VLAN2QID			0x0304

	VLAN5QID				VLAN4QID			0x0308

	VLAN7QID				VLAN6QID			0x030C

	VLAN9QID				VLAN8QID			0x0310

	VLAN11QID				VLAN10QID			0x0314

	VLAN13QID				VLAN12QID			0x0318

	VLAN15QID				VLAN14QID			0x031C

	VLAN17QID				VLAN16QID			0x0320

	VLAN19QID				VLAN18QID			0x0324

	VLAN21QID				VLAN20QID			0x0328

	VLAN23QID				VLAN22QID			0x032C

	VLAN25QID				VLAN24QID			0x0330

	VLAN27QID				VLAN26QID			0x0334

	VLAN29QID				VLAN28QID			0x0338

	VLAN31QID				VLAN30QID			0x033C

	VLAN33QID				VLAN32QID			0x0340

	VLAN35QID				VLAN34QID			0x0344

20	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 20

Texas Instruments TNETX4090 specifications VLAN1QID VLAN0QID

Contents

Description MII MAC MIIMAC Eeprom CPU I/F DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball Name Reset Sdma SAD0 Terminal Functions Jtag interfaceControl logic interface Terminal Internal Description Name RESISTOR² 100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5 Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 Pulldown M00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4 MII management interface Rdram interface DIO interface Eeprom interface 100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090 VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail Port no Head Statistic Tail 0x90Ex DMA Interface Signals Signal DescriptionAddress-Lookup Statistics Receiving/transmitting management frames State of DIO signal terminals during hardware reset DIO Interface During Hardware ResetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port Vlan ID FCSTpid TCI CRC TNETX4090 PHY management interface Full-duplex NM portNM bandwidth and priority Interrupt processing MAC interface Adaptive performance optimization APO Interframe gap enforcementBackoff Receive versus transmit priority 10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Duplex Negotiation in MII Mode Port 8 Pause Negotiation in MII ModeFull-duplex hardware flow control Outcome M08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission Transmit Pretag Bit Definitions Pretag on receptionLearning Format Receive Pretag Bit Definitions BIT Name Function Directed Format Receive Pretag Bit Definitions Ring-cascade topologyRXD Flow COL TXD TNETX4090 RXD Flow COL TXD M08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Compatibility with future device revisions Port LED StatesCollision LED States State Display PCS duplex LED LED Status Bit Definitions and Shift OrderLamp test Multi-LED display BUS Enable GND BUS Ctrl Rdram SIN BUS Enable GND Rdram BUS Ctrl SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDD Jtag Instruction Opcodes Highz instructionRacbist instruction Jtag Bist Status Iale Frame routingVlan support Address maintenance Ieee Std 802.1Q tags ± receptionIeee Std 802.1Q header ± transmission Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source port Port trunking example Trunk Group 0 Port Membership Trunk0Ports RegisterTrunk Group 1 Port Membership Trunk1Ports Register Extended port awareness Flow control Other flow-control mechanisms Hardware flow controlMulticast limit System test capabilities Reading Rdram Internal wrap test Duplex wrap test PHY TNETX4090 Recommended operating conditions MIN NOM MAX Unit Timing requirements over recommended operating conditions Jtag interface Control signalsReset see Figure Physical medium attachment interface port Receive PMA receive see Figure Transmit PMA transmit see Figure Gmii transmit see Figure Gmii portGmii receive see Figure PMA and Gmii clock see Figure Gmii Clock MII ports 0±8 MII receive see Figure MII transmit see Figure MII clock see Figure Rdram interface Rdram see FigureDtxclk Drxclk Dbusctrl Dbusen SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Eeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOH VOL TTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TNETX4090GGP Obsolete BGA TBD Important Notice