VLAN37QID VLAN36QID | Texas Instruments TNETX4090 instruction

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

Table 2. DIO Internal Register Address Map (Continued)

BYTE 3		BYTE 2		BYTE 1		BYTE 0	DIO
BYTE 3		BYTE 2		BYTE 1		BYTE 0	ADDRESS
							ADDRESS

VLAN37QID					VLAN36QID		0x0348

VLAN39QID					VLAN38QID		0x034C

VLAN41QID					VLAN40QID		0x0350

VLAN43QID					VLAN42QID		0x0354

VLAN45QID					VLAN44QID		0x0358

VLAN47QID					VLAN46QID		0x035C

VLAN49QID					VLAN48QID		0x0360

VLAN51QID					VLAN50QID		0x0364

VLAN53QID					VLAN52QID		0x0368

VLAN55QID					VLAN54QID		0x036C

VLAN57QID					VLAN56QID		0x0370

VLAN59QID					VLAN58QID		0x0374

VLAN61QID					VLAN60QID		0x0378

VLAN63QID					VLAN62QID		0x037C

Port1QTag					Port0QTag		0x0380

Port3QTag					Port2QTag		0x0384

Port5QTag					Port4QTag		0x0388

Port7QTag					Port6QTag		0x038C

Reserved					Port8QTag		0x0390

			Reserved				0x0394±0x03FC

Port1Status					Port0Status		0x0400

Port3Status					Port2Status		0x0404

Port5Status					Port4Status		0x0408

Port7Status					Port6Status		0x040C

Reserved					Port8Status		0x0410

			Reserved				0x0414±0x043C

FindNode[23:16]		FindNode[31:24]		FindNode[39:32]		FindNode[47:40]	0x0440

FindVLAN		FindControl		FindNode[7:0]		FindNode[15:8]	0x0444

			FindPort				0x0448

NewNode[23:16]		NewNode[31:24]		NewNode[39:32]		NewNode[47:40]	0x044C

Reserved				NewNode[7:0]		NewNode[15:8]	0x0450

NewVLAN					NewPort		0x0454

AddNode[23:16]		AddNode[31:24]		AddNode[39:32]		AddNode[47:40]	0x0458

AddVLAN		AddDelControl		AddNode[7:0]		AddNode[15:8]	0x045C

			AddPort				0x0460

AgedNode[23:16]		AgedNode[31:24]		AgedNode[39:32]		AgedNode[47:40]	0x0464

AgedVLAN		AgedPort		AgedNode[7:0]		AgedNode[15:8]	0x0468

DelNode[23:16]		DelNode[31:24]		DelNode[39:32]		DelNode[47:40]	0x046C

DelVLAN		DelPort		DelNode[7:0]		DelNode[15:8]	0x0470

AgingCounter					NumNodes		0x0474

			Reserved				0x0478±0x0540

		XMultiGroup17					0x0544

		XMultiGroup18					0x0548

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

21

Image 21

Texas Instruments TNETX4090 specifications VLAN37QID VLAN36QID

Contents

Description MAC MII MIIMAC Eeprom CPU I/F DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted Alphabetically Reset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR² M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii mode Terminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7 M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch MII management interface Rdram interface Eeprom interface DIO interface Power supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic Tail Signal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management frames DIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port FCS Vlan IDTpid TCI CRC TNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processing MAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit priority Speed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control Outcome Pretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name Function Ring-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXD Switch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State Display LED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED display BUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDD Highz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist Status Frame routing Vlan supportIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharing Trunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awareness Flow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilities Internal wrap test Reading Rdram PHY TNETX4090 Duplex wrap test MIN NOM MAX Unit Recommended operating conditions Jtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port Receive PMA transmit see Figure Transmit Gmii port Gmii receive see FigureGmii transmit see Figure Gmii Clock PMA and Gmii clock see Figure MII receive see Figure MII ports 0±8 MII clock see Figure MII transmit see Figure Rdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl Dbusen DIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see Figure Eeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOL VOH TTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGA Important Notice