M00RENEG M01RENEG | Texas Instruments TNETX4090 specification

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

						Terminal Functions (Continued)
10-/100-Mbit/s MAC interface (MII mode) (ports 0±7) (continued)

	TERMINAL			I/O	INTERNAL		DESCRIPTION
	NAME		NO.	I/O	RESISTOR		DESCRIPTION
	NAME		NO.		RESISTOR

			C26
	M00_RENEG		C26
	M01_RENEG		D26
	M02_RENEG		D1				Renegotiate. Indicates to the attached PHY device that this port wishes to renegotiate a new
	M03_RENEG		C1	O	None
	M03_RENEG		C1	O	None		configuration.
	M04_RENEG		F3				configuration.
	M04_RENEG		F3
	M05_RENEG		F2
	M06_RENEG		AA3

	M00_RXDV		D19
	M01_RXDV		A16
	M02_RXDV		C9				Receive data valid. Indicates data on Mxx_RXD7±Mxx_RxD0. is valid. This signal is
	M03_RXDV		C4	I	Pulldown
	M04_RXDV		J2	I	Pulldown		synchronous to Mxx_RCLK.
	M04_RXDV		J2				synchronous to Mxx_RCLK.
	M05_RXDV		T4
	M06_RXDV		W1
	M07_RXDV		AC8

	M00_RXD3		D20
	M00_RXD2		C20
	M00_RXD1		B20
	M00_RXD0		A20
	M01_RXD3		D15
	M01_RXD2		C15
	M01_RXD1		B15
	M01_RXD0		A15
	M02_RXD3		D10
	M02_RXD2		C10
	M02_RXD1		B10				Receive data. Nibble receive data from the attached PHY device. Data on these signals is
	M02_RXD0		A10
	M02_RXD0		A10				synchronous to Mxx_RCLK. When Mxx_RXDV and Mxx_RXER are low, these terminals are
	M03_RXD3		D5
	M03_RXD3		D5				sampled the cycle before Mxx_LINK goes high to configure the port, based on capabilities
	M03_RXD2		C5
	M03_RXD2		C5				negotiated by the attached PHY device as follows:
	M03_RXD1		B5				negotiated by the attached PHY device as follows:
	M03_RXD1		B5				± Mxx_RXD0 indicates full-duplex mode when high; half duplex when low, and sets
	M03_RXD0		A5	I	Pullup
	M03_RXD0		A5				duplex in PortxStatus.
	M04_RXD3		K3				duplex in PortxStatus.
	M04_RXD3		K3				± Mxx_RXD1 indicates IEEE Std 802.3 pause frame support when high; no pause
	M04_RXD2		K2
	M04_RXD2		K2				when low, and sets pause in PortxStatus.
	M04_RXD1		K1				when low, and sets pause in PortxStatus.
	M04_RXD1		K1				± Mxx_RXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, and sets speed in
	M04_RXD0		J1
	M04_RXD0		J1				PortxStatus.
	M05_RXD3		R4				PortxStatus.
	M05_RXD3		R4				± Mxx_RXD3 is unused and is ignored.
	M05_RXD2		R3				± Mxx_RXD3 is unused and is ignored.
	M05_RXD2		R3
	M05_RXD1		R2
	M05_RXD0		R1
	M06_RXD3		Y4
	M06_RXD2		Y3
	M06_RXD1		Y2
	M06_RXD0		Y1
	M07_RXD3		AC7
	M07_RXD2		AD7
	M07_RXD1		AE7
	M07_RXD0		AF7

12	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

Image 12

Texas Instruments TNETX4090 specifications M00RENEG M01RENEG

Contents

Description MII MAC MIIMAC Eeprom CPU I/F DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball Name Reset Sdma SAD0 Terminal Functions Jtag interfaceControl logic interface Terminal Internal Description Name RESISTOR² 100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5 Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 Pulldown M00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4 MII management interface Rdram interface DIO interface Eeprom interface Power supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090 VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports Port no Head Statistic Tail 0x90Ex DMA Interface Signals Signal DescriptionAddress-Lookup Statistics Receiving/transmitting management frames State of DIO signal terminals during hardware reset DIO Interface During Hardware ResetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port Vlan ID FCSTpid TCI CRC TNETX4090 PHY management interface Full-duplex NM portNM bandwidth and priority Interrupt processing MAC interface Adaptive performance optimization APO Interframe gap enforcementBackoff Receive versus transmit priority 10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Duplex Negotiation in MII Mode Port 8 Pause Negotiation in MII ModeFull-duplex hardware flow control Outcome Pretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Transmit Pretag Bit Definitions Pretag on receptionLearning Format Receive Pretag Bit Definitions BIT Name Function Directed Format Receive Pretag Bit Definitions Ring-cascade topologyRXD Flow COL TXD TNETX4090 RXD Flow COL TXD Switch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Compatibility with future device revisions Port LED StatesCollision LED States State Display PCS duplex LED LED Status Bit Definitions and Shift OrderLamp test Multi-LED display BUS Enable GND BUS Ctrl Rdram SIN BUS Enable GND Rdram BUS Ctrl SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDD Jtag Instruction Opcodes Highz instructionRacbist instruction Jtag Bist Status Frame routing Vlan supportIale Address maintenance Ieee Std 802.1Q tags ± receptionIeee Std 802.1Q header ± transmission Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source port Port trunking example Trunk Group 0 Port Membership Trunk0Ports RegisterTrunk Group 1 Port Membership Trunk1Ports Register Extended port awareness Flow control Other flow-control mechanisms Hardware flow controlMulticast limit System test capabilities Reading Rdram Internal wrap test Duplex wrap test PHY TNETX4090 Recommended operating conditions MIN NOM MAX Unit Jtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions Physical medium attachment interface port Receive PMA receive see Figure Transmit PMA transmit see Figure Gmii port Gmii receive see FigureGmii transmit see Figure PMA and Gmii clock see Figure Gmii Clock MII ports 0±8 MII receive see Figure MII transmit see Figure MII clock see Figure Rdram interface Rdram see FigureDtxclk Drxclk Dbusctrl Dbusen DIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Eeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOH VOL TTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TNETX4090GGP Obsolete BGA TBD Important Notice