TNETX4090
ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999
DIO interface description (continued)
Table 5. Address-Lookup Statistics
PORT NO. | HEAD | STATISTIC |
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N/A | 0x9200±0x9FFC | Reserved |
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N/A | 0xA000 | Unknown unicast destination addresses |
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N/A | 0xA004 | Unknown multicast destination addresses |
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N/A | 0xA008 | Unknown source addresses |
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N/A | 0xA00C±0xFFFC | Reserved |
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When accessing the statistics values from the DIO port, it is necessary to perform four
To provide ease of use with both big- and
receiving/transmitting management frames
Frames originating within the host are written to the NM port via the NMRxControl and NMData registers. Once a frame has been fully written, it is then received by the switch and routed to the destination port(s).
Frames that were routed to this port from any of the switch ports are placed in a queue until the host is ready to read them via the NMTxControl and NMData registers. They then are effectively transmitted out of the switch.
SDMA can be used to transmit or receive management frames (the SAD1±SAD0 terminals are ignored when SDMA is asserted) (see Table 6). When SDMA is asserted, the switch uses the value in the DMAAddress register instead of the DIO address registers to access frame data (this also can be used to access the switch statistics). STXRDY and SRXRDY, the interrupts, freebuffs, eof, sof, and iof mechanisms can be used, as desired, to prevent unwanted stalls on the DIO bus during busy periods.
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| Table 6. DMA Interface Signals |
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| SIGNAL | DESCRIPTION | |
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| Automatically sets up DIO address using the DMAAddress register |
| SDMA |
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| STXRDY | Indicates that at least one data frame buffer can be read by the management CPU | |
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| SRXRDY | Indicates that the management CPU can write a frame of any size up to 1535 bytes | |
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