Jtag interface Control signals | Texas Instruments TNETX4090

TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

electrical characteristics over recommended operating conditions (unless otherwise noted)

	PARAMETER	TEST CONDITIONS	MIN	TYP MAX	UNIT

VOH	High-level output voltage	IOH = rated	VDD(3.3)±0.5		V
VOL	Low-level output voltage	IOL = rated		0.5	V
IOZ	High-impedance-state output	VO = VDD or GND		±10	∝A
IOZ	current	VO = VDD or GND		±10	∝A
	current

IIH	High-level input current	VI = VIH		1	∝A
IIL	Low-level input current	VI = VIL		±1	∝A
VOHR	High-level output voltage (RSL)	IOH	2	VDD	V
VOLR	Low-level output voltage (RSL)		0	0.4	V
IDD(2.5V)		VDD(2.5V) = max,		1.5
IDD(2.5V)		DTX_CLK and DRX_CLKf = 83.33 MHz		1.5
		DTX_CLK and DRX_CLKf = 83.33 MHz

IDD(3.3V)	Supply current	VDD(3.3V) = max,		0.5	A
IDD(3.3V)	Supply current	DTX_CLK and DRX_CLKf = 83.33 MHz		0.5	A
		DTX_CLK and DRX_CLKf = 83.33 MHz

IDD(2.5)		VDD(2.5) = max,		0.175
IDD(2.5)		DTX_CLK and DRX_CLKf = 83.33 MHz		0.175
		DTX_CLK and DRX_CLKf = 83.33 MHz

Ci	Capacitance, input			6	pF
Co	Capacitance, output			6	pF

timing requirements over recommended operating conditions

JTAG interface

control signals

RESET (see Figure 15)

NO.

1	tw(RESETP)	Pulse duration,		RESET	low at power up
1	tw(RESET)	Pulse duration,	RESET		low at other times

MIN MAX UNIT

100∝s

4tcycle

1

RESET

Figure 15. RESET

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

61

Image 61

Texas Instruments TNETX4090 Timing requirements over recommended operating conditions, Jtag interface Control signals

Contents

Description MAC MII MIIMAC Eeprom CPU I/F DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted Alphabetically Reset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR² M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii mode Terminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7 M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch MII management interface Rdram interface Eeprom interface DIO interface LED interface Power supply100-/1000-Mbit/s port PCS LED interface DIO Internal Register Address Map DIO interface descriptionByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Tail Port StatisticsPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic Tail Signal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management frames DIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port FCS Vlan IDTpid TCI CRC TNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processing MAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit priority Speed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control Outcome Pretag on transmission Pretagging and extended port awarenessM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name Function Ring-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXD Ring-Topology Connectivity Switch TerminalM08GTCLK M08TXEN M08RXDV Edio TNETX4090 Eclk SCL SDAGND Interaction of Eeprom load with the SIO register Outcome Stop Load Initd ² Fault LED EclkSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State Display LED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED display BUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDD Highz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist Status Vlan support Frame routingIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharing Trunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awareness Flow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilities Internal wrap test Reading Rdram PHY TNETX4090 Duplex wrap test MIN NOM MAX Unit Recommended operating conditions Reset see Figure Jtag interface Control signalsTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port Receive PMA transmit see Figure Transmit Gmii receive see Figure Gmii portGmii transmit see Figure Gmii Clock PMA and Gmii clock see Figure MII receive see Figure MII ports 0±8 MII clock see Figure MII transmit see Figure Rdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl Dbusen DIO and DMA writes see Figure DIO interfaceSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see Figure Eeprom writes see Figure Eeprom interfaceEeprom reads see Figure LED see Figure LED interfaceLedclk Leddata VOL VOH TTL Output Macro Propagation-Delay-Time Voltage Waveforms 50% Lvcmos VDD VOHVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGA Important Notice