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Texas Instruments TNETX4090 TTL Output Macro Propagation-Delay-Time Voltage Waveforms

Models: TNETX4090

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TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

PARAMETER MEASUREMENT INFORMATION

			tr
	Input		80%	80%
	Input	20%	47%	47%
			47%	47%

	Out-of-Phase			47%
	Output			47%
	Output
		tPHL
		tPLH
	In-Phase			47%
	Output			47%
	Output

tf

VDD

20% 0

tPHL

VOH

47%

VOL

tPHL

VOH

47%

VOL

Figure 33. Internal Push/Pull Output Propagation-Delay-Time Voltage Waveforms

		tr
CMOS-Level		80%	80%
Input		80%	80%
Input	20%	47%	47%
	20%
CMOS tPLH
LVCMOS/TTL		50%
Output		50%
Output		1.3 V
TTL tPLH

tf

VDD

20% 0

CMOS tPHL

VOH

50%

1.3 V VOL

TTL tPHL

Figure 34. TTL Output Macro Propagation-Delay-Time Voltage Waveforms

74	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Texas Instruments TNETX4090 specifications TTL Output Macro Propagation-Delay-Time Voltage Waveforms

Contents

Description MAC Eeprom CPU I/F MIIMAC MII DMA PCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal-to-Ball Mapping Signal Names Sorted Alphabetically Signal Ball Name Reset Sdma SAD0 Control logic interface Terminal FunctionsJtag interface Terminal Internal Description Name RESISTOR² 100-/1000-Mbit/s MAC interface Gmii mode M08TXD7 M08TXD6 M08TXD5 Terminal Internal Description Name Resistor Port to not support pause frames 10-/100-Mbit/s MAC interface MII mode ports 0±7 Pulldown M00RENEG M01RENEG ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET Switch M04TCLK M05TCLK M06TCLK M07TCLK AD4 MII management interface Rdram interface DIO interface Eeprom interface 100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET TNETX4090 VLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail Port no Head Statistic Tail 0x90Ex Address-Lookup Statistics DMA Interface SignalsSignal Description Receiving/transmitting management frames DIO Interface State During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM port Tpid TCI Vlan IDFCS CRC TNETX4090 NM bandwidth and priority PHY management interfaceFull-duplex NM port Interrupt processing MAC interface Backoff Adaptive performance optimization APOInterframe gap enforcement Receive versus transmit priority 10-/100-Mbit/s MII ports 0±7 Speed, duplex, and flow-control negotiation 100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Full-duplex hardware flow control Port 8 Duplex Negotiation in MII ModePort 8 Pause Negotiation in MII Mode Outcome M08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission Learning Format Receive Pretag Bit Definitions Transmit Pretag Bit DefinitionsPretag on reception BIT Name Function RXD Flow COL TXD Directed Format Receive Pretag Bit DefinitionsRing-cascade topology TNETX4090 RXD Flow COL TXD M08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Collision LED States Compatibility with future device revisionsPort LED States State Display Lamp test PCS duplex LEDLED Status Bit Definitions and Shift Order Multi-LED display TNETX4090 VCC NC Txclk Vref Rxclk VDD BUS Enable GND BUS Ctrl Rdram SINBUS Enable GND Rdram BUS Ctrl SIN Sout SCHAIN0 Txclk Vref Rxclk VDD Racbist instruction Jtag Instruction OpcodesHighz instruction Jtag Bist Status Iale Frame routingVlan support Ieee Std 802.1Q header ± transmission Address maintenanceIeee Std 802.1Q tags ± reception Spanning-tree support Aging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Port trunking/load sharing Removal of source port Trunk Group 1 Port Membership Trunk1Ports Register Port trunking exampleTrunk Group 0 Port Membership Trunk0Ports Register Extended port awareness Flow control Multicast limit Other flow-control mechanismsHardware flow control System test capabilities Reading Rdram Internal wrap test Duplex wrap test PHY TNETX4090 Recommended operating conditions MIN NOM MAX Unit Timing requirements over recommended operating conditions Jtag interface Control signalsReset see Figure Physical medium attachment interface port Receive PMA receive see Figure Transmit PMA transmit see Figure Gmii transmit see Figure Gmii portGmii receive see Figure PMA and Gmii clock see Figure Gmii Clock MII ports 0±8 MII receive see Figure MII transmit see Figure MII clock see Figure Dtxclk Drxclk Rdram interfaceRdram see Figure Dbusctrl Dbusen SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure DIO and DMA reads see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Eeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOH VOL TTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TNETX4090GGP Obsolete BGA TBD Important Notice