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Texas Instruments TNETX4090 specifications PMA and Gmii clock see Figure, Gmii Clock

Models: TNETX4090

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TNETX4090

ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

PMA and GMII clock (see Figure 20)

NO.			MIN MAX	UNIT

1	tr(Mxx_GCLK)	Pulse width low, Mxx_RFCLK	2.5	ns
2	th(Mxx_GCLK)	Pulse width high, Mxx_RFCLK	2.5	ns
3	tw(Mxx_GCLK)	Cycle time, Mxx_RFCLK	8	ns

PMA and GMII clock (see Figure 20)

NO.			MIN	MAX	UNIT

1	tr(Mxx_GCLK)	Rise time, Mxx_RFCLK		1	ns
2	tf(Mxx_GCLK)	Fall time, Mxx_RFCLK		1	ns
3	Accuracy		100		PPM

	duty cycle		40%	60%

²tr and tf are measured between 20% and 80%, VDD(3.3-V)= min, output load (GTCLK) = 20pf.

3

1 2

Mxx_RFCLK

Figure 20. GMII Clock

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Texas Instruments TNETX4090 specifications PMA and Gmii clock see Figure, Gmii Clock

Contents

Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interface100-/1000-Mbit/s port PCS LED interface Power supplyLED interface Byte DIO Address DIO interface descriptionDIO Internal Register Address Map TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port no Head Statistic Even ODD Ports Port StatisticsTail 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomeM08GTCLK M08TXEN Pretagging and extended port awarenessPretag on transmission Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDM08GTCLK M08TXEN M08RXDV Switch TerminalRing-Topology Connectivity GND SCL SDAEdio TNETX4090 Eclk Summary of Eeprom load outcomes Outcome Stop Load Initd ² Fault LED EclkInteraction of Eeprom load with the SIO register Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusIale Frame routingVlan support Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsTiming requirements over recommended operating conditions Jtag interface Control signalsReset see Figure PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii transmit see Figure Gmii portGmii receive see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint DIO interfaceDIO and DMA writes see Figure SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom reads see Figure Eeprom interfaceEeprom writes see Figure Ledclk Leddata LED interfaceLED see Figure VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms VOL VDD VDD VOH50% Lvcmos Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice