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Texas Instruments TNETX4090 specifications Terminal Internal Description Name Resistor

Models: TNETX4090

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							TNETX4090
				ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SWITCH
							SPWS044E ± DECEMBER 1997 ± REVISED AUGUST 1999

					Terminal Functions (Continued)
100-/1000-Mbit/s MAC interface [physical media attachment (PMA) mode]

	TERMINAL		I/O	INTERNAL			DESCRIPTION
	NAME		I/O	RESISTOR			DESCRIPTION
	NAME			RESISTOR

	M08_COL		I	Pulldown	Receive byte clock 1. M08_COL is used to input receive byte clock 1 from the attached SERDES
	M08_COL		I	Pulldown	device.
					device.

	M08_CRS		I	Pulldown	Unused. This terminal can be left unconnected.

	M08_EWRAP		O	None	Enable wrap. Output to attached SERDES device used to enable loopback testing of that device.
	M08_EWRAP		O	None	M08_EWRAP is asserted when loopback in PCSxControl = 1.
					M08_EWRAP is asserted when loopback in PCSxControl = 1.

	M08_GTCLK		O	None	Transmit clock. Transmit clock output to attached SERDES device.

					Signal detect. This can be connected to the signal detect output from the external SERDES device.
	M08_LINK		I	Pulldown	± If M08_LINK = 0, there is no signal.
					± If M08_LINK = 1, signal is present.

					Lock to reference.		is asserted low during hard reset or when lckref in PortxControl = 1.
						M08_LREF
	M08_LREF		O	None		M08_LREF
	M08_LREF		O	None	It is used by the external SERDES device to lock to its reference clock.


	M08_RCLK		I	Pullup	Receive byte clock 0. M08_RCLK is used to input receive byte clock 0 from the attached SERDES
	M08_RCLK		I	Pullup	device.
					device.

					Reference clock. Reference clock, used as the clock source for the transmit side of this port and
	M08_RFCLK		I	Pullup	to generate M08_GTCLK. M08_RFCLK provides the clock source for the entire internal PCS
					sublayer.

	M08_RXD7
	M08_RXD6
	M08_RXD5				Receive data. Least significant eight bits of the 10-bit receive code group. Even-numbered code
	M08_RXD4		I	Pullup
	M08_RXD3		I	Pullup	groups are latched with M08_COL, and odd-numbered code groups are latched with M08_RCLK.
	M08_RXD3
	M08_RXD2
	M08_RXD1
	M08_RXD0

					Receive data valid. M08_RXDV is used to receive the 9th bit of the 10-bit PMA code groups.
	M08_RXDV		I	Pulldown	Even-numbered code groups are latched with M08_COL, and odd-numbered code groups are
					latched with M08_RCLK.

					Receive error. M08_RXER is used to receive the 10th bit of the 10-bit PMA code groups.
	M08_RXER		I	Pulldown	Even-numbered code groups are latched with M08_COL, and odd-numbered code groups are
					latched with M08_RCLK.

	M08_TXD7
	M08_TXD6
	M08_TXD5				Transmit data. Least significant eight bits of the 10-bit transmit code group. Data on these signals
	M08_TXD4		O	None
	M08_TXD3		O	None	is synchronous to M08_GTCLK.
	M08_TXD3				is synchronous to M08_GTCLK.
	M08_TXD2
	M08_TXD1
	M08_TXD0

	M08_TXEN		O	None	Transmit enable. M08_TXEN is used to transmit the 9th bit of the 10-bit PMA code groups. Data
	M08_TXEN		O	None	on this signal is synchronous to M08_GTCLK.
					on this signal is synchronous to M08_GTCLK.

	M08_TXER		O	None	Transmit error. M08_TXER is used to transmit the 10th bit of the 10-bit PMA code groups. Data on
	M08_TXER		O	None	this signal is synchronous to M08_GTCLK.
					this signal is synchronous to M08_GTCLK.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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Texas Instruments TNETX4090 specifications Terminal Internal Description Name Resistor

Contents

Description MAC MII MIIMAC Eeprom CPU I/F DMAPCS Duplex LED Rdram Interface Jtag Interface GGP Package Bottom View Signal Ball Name Signal-to-Ball Mapping Signal Names Sorted AlphabeticallyReset Sdma SAD0 Jtag interface Terminal FunctionsControl logic interface Terminal Internal Description Name RESISTOR²M08TXD7 M08TXD6 M08TXD5 100-/1000-Mbit/s MAC interface Gmii modeTerminal Internal Description Name Resistor Port to not support pause frames Pulldown 10-/100-Mbit/s MAC interface MII mode ports 0±7M00RENEG M01RENEG M04TCLK M05TCLK M06TCLK M07TCLK AD4 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNET SwitchMII management interface Rdram interface Eeprom interface DIO interfacePower supply LED interface100-/1000-Mbit/s port PCS LED interface DIO interface description DIO Internal Register Address MapByte DIO Address TNETX4090 ThunderSWITCH II 9-PORT 100-/1000-MBIT/S ETHERNETVLAN1QID VLAN0QID VLAN37QID VLAN36QID TNETX4090 PCS8Status PCS8Control 0x0700 DIO interface description Port Statistics TailPort no Head Statistic Even ODD Ports 0x90Ex Port no Head Statistic TailSignal Description DMA Interface SignalsAddress-Lookup Statistics Receiving/transmitting management framesDIO Interface During Hardware Reset State of DIO signal terminals during hardware resetDIO Interface State During Hardware Reset Ieee Std 802.1Q Vlan tags on the NM portFCS Vlan IDTpid TCI CRCTNETX4090 Full-duplex NM port PHY management interfaceNM bandwidth and priority Interrupt processingMAC interface Interframe gap enforcement Adaptive performance optimization APOBackoff Receive versus transmit prioritySpeed, duplex, and flow-control negotiation 10-/100-Mbit/s MII ports 0±7100-Mbit/s Port Negotiation With the TNETE2104 100-/1000-Mbit/s PHY interface port Port 8 Pause Negotiation in MII Mode Port 8 Duplex Negotiation in MII ModeFull-duplex hardware flow control OutcomePretagging and extended port awareness Pretag on transmissionM08GTCLK M08TXEN Pretag on reception Transmit Pretag Bit DefinitionsLearning Format Receive Pretag Bit Definitions BIT Name FunctionRing-cascade topology Directed Format Receive Pretag Bit DefinitionsRXD Flow COL TXD TNETX4090 RXD Flow COL TXDSwitch Terminal Ring-Topology ConnectivityM08GTCLK M08TXEN M08RXDV SCL SDA Edio TNETX4090 EclkGND Outcome Stop Load Initd ² Fault LED Eclk Interaction of Eeprom load with the SIO registerSummary of Eeprom load outcomes Port LED States Compatibility with future device revisionsCollision LED States State DisplayLED Status Bit Definitions and Shift Order PCS duplex LEDLamp test Multi-LED displayBUS Enable GND Rdram BUS Ctrl SIN BUS Enable GND BUS Ctrl Rdram SINTNETX4090 VCC NC Txclk Vref Rxclk VDD Sout SCHAIN0 Txclk Vref Rxclk VDDHighz instruction Jtag Instruction OpcodesRacbist instruction Jtag Bist StatusFrame routing Vlan supportIale Ieee Std 802.1Q tags ± reception Address maintenanceIeee Std 802.1Q header ± transmission Spanning-tree supportAging algorithms Frame-Routing Algorithm SPWS044E ± December 1997 ± Revised August Port routing code Removal of source port Port trunking/load sharingTrunk Group 0 Port Membership Trunk0Ports Register Port trunking exampleTrunk Group 1 Port Membership Trunk1Ports Register Extended port awarenessFlow control Hardware flow control Other flow-control mechanismsMulticast limit System test capabilitiesInternal wrap test Reading RdramPHY TNETX4090 Duplex wrap testMIN NOM MAX Unit Recommended operating conditionsJtag interface Control signals Reset see FigureTiming requirements over recommended operating conditions PMA receive see Figure Physical medium attachment interface port ReceivePMA transmit see Figure TransmitGmii port Gmii receive see FigureGmii transmit see Figure Gmii Clock PMA and Gmii clock see FigureMII receive see Figure MII ports 0±8MII clock see Figure MII transmit see FigureRdram see Figure Rdram interfaceDtxclk Drxclk Dbusctrl DbusenDIO interface DIO and DMA writes see FigureSCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy Sint SCS Srnw SAD1±SAD0 Sdma SDATA7± SDATA0 Srdy DIO and DMA reads see FigureEeprom interface Eeprom writes see FigureEeprom reads see Figure LED interface LED see FigureLedclk Leddata VOL VOHTTL Output Macro Propagation-Delay-Time Voltage Waveforms VDD VOH 50% LvcmosVOL VDD Mechanical Data TBD TNETX4090GGP Obsolete BGAImportant Notice