CY7C65113C
Document #: 38-08002 Rev. *D Page 24 of 49
14.0 Interrupts
Interrupts are generated by GPIO pins, internal timers, I2C-compatible operation, internal USB hub and USB traffic conditions.
All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a
‘1’ to a bit position enables the interrupt associated with that bit position.
Bit 0 : USB Bus RST Interrupt Enable
1 = Enable Interrupt on a USB Bus Reset; 0 = Disable interrupt on a USB Bus Reset (Refer to section 14.3).
Bit 1 :128-µs Interrupt Enable
1 = Enable Timer interrupt every 128 µs; 0 = Disable Timer Interrupt for every 128 µs.
Bit 2 : 1.024-ms Interrupt Enable
1 = Enable Timer interrupt every 1.024 ms; 0 = Disable Timer Interrupt every 1.024 ms.
Bit 3 : USB Hub Interrupt Enable
1 = Enable Interrupt on a Hub status change; 0 = Disable interrupt due to hub status change. (Refer to section 14.6.)
Bit 4 : Reserved.
Bit 5 : GPIO Interrupt Enable
1 = Enable Interrupt on falling/rising edge on any GPIO; 0 = Disable Interrupt on falling/rising edge on any GPIO (Refer to
section 14.7, 9.1 and 9.2.).
Bit 6 : I2C Interrupt Enable
1 = Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 14.8.)
Bit 7 : Reserved.
Bit 0: EPA0 Interrupt Enable
1 = Enable Interrupt on data activity through endpoint A0; 0 = Disable Interrupt on data activity through endpoint A0
Bit 1: EPA1 Interrupt Enable
1 = Enable Interrupt on data activity through endpoint A1; 0 = Disable Interrupt on data activity through endpoint A1
Bit 2: EPA2 Interrupt Enable
1 = Enable Interrupt on data activity through endpoint A2; 0 = Disable Interrupt on data activity through endpoint A2.
Bit 3: EPB0 Interrupt Enable
1 = Enable Interrupt on data activity through endpoint B0; 0 = Disable Interrupt on data activity through endpoint B0
Bit 4: EPB1 Interrupt Enable
1 = Enable Interrupt on data activity through endpoint B1; 0 = Disable Interrupt on data activity through endpoint B1
Bit [7..5] : Reserved
Global Interrupt Enable Register Address 0X20
Bit # 76543210
Bit Name Reserved I2C Interrupt
Enable
GPIO
Interrupt
Enable
Reserved USB Hub
Interrupt
Enable
1.024-ms
Interrupt
Enable
128-µs
Interrupt
Enable
USB Bus
RST
Interrupt
Enable
Read/Write – R/W R/W - R/W R/W R/W R/W
Reset –00X0000
Figure 14-1. Global Interrupt Enable Register
USB Endpoint Interrupt Enable Address 0X21
Bit # 76543210
Bit Name Reserved Reserved Reserved EPB1
Interrupt
Enable
EPB0
Interrupt
Enable
EPA2
Interrupt
Enable
EPA1
Interrupt
Enable
EPA0
Interrupt
Enable
Read/Write – – – R/W R/W R/W R/W R/W
Reset –––00000
Figure 14-2. USB Endpoint Interrupt Enable Register
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