Cypress CY7C65113C manual Interrupts, Global Interrupt Enable Register Address

CY7C65113C

14.0Interrupts

Interrupts are generated by GPIO pins, internal timers, I2C-compatible operation, internal USB hub and USB traffic conditions. All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a ‘1’ to a bit position enables the interrupt associated with that bit position.

Global Interrupt Enable Register							Address 0X20
Bit #	7	6	5	4	3	2	1	0
Bit Name	Reserved	I2C Interrupt	GPIO	Reserved	USB Hub	1.024-ms	128-∝s	USB Bus
		Enable	Interrupt		Interrupt	Interrupt	Interrupt	RST
			Enable		Enable	Enable	Enable	Interrupt
								Enable
Read/Write	–	R/W	R/W	-	R/W	R/W	R/W	R/W
Reset	–	0	0	X	0	0	0	0
		Figure 14-1. Global Interrupt Enable Register

Bit 0 : USB Bus RST Interrupt Enable

1 = Enable Interrupt on a USB Bus Reset; 0 = Disable interrupt on a USB Bus Reset (Refer to section 14.3). Bit 1 :128-∝s Interrupt Enable

1 = Enable Timer interrupt every 128 ∝s; 0 = Disable Timer Interrupt for every 128 ∝s. Bit 2 : 1.024-ms Interrupt Enable

1 = Enable Timer interrupt every 1.024 ms; 0 = Disable Timer Interrupt every 1.024 ms. Bit 3 : USB Hub Interrupt Enable

1 = Enable Interrupt on a Hub status change; 0 = Disable interrupt due to hub status change. (Refer to section 14.6.)

Bit 4 : Reserved.

Bit 5 : GPIO Interrupt Enable

1 = Enable Interrupt on falling/rising edge on any GPIO; 0 = Disable Interrupt on falling/rising edge on any GPIO (Refer to section 14.7, 9.1 and 9.2.).

Bit 6 : I2C Interrupt Enable

1 = Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 14.8.)

Bit 7 : Reserved.

USB Endpoint Interrupt Enable								Address 0X21
Bit #	7	6	5	4	3	2	1		0
Bit Name	Reserved	Reserved	Reserved	EPB1	EPB0	EPA2	EPA1		EPA0
				Interrupt	Interrupt	Interrupt	Interrupt		Interrupt
				Enable	Enable	Enable	Enable		Enable
Read/Write	–	–	–	R/W	R/W	R/W	R/W		R/W
Reset	–	–	–	0	0	0	0		0

Figure 14-2. USB Endpoint Interrupt Enable Register

Bit 0: EPA0 Interrupt Enable

1 = Enable Interrupt on data activity through endpoint A0; 0 = Disable Interrupt on data activity through endpoint A0 Bit 1: EPA1 Interrupt Enable

1 = Enable Interrupt on data activity through endpoint A1; 0 = Disable Interrupt on data activity through endpoint A1 Bit 2: EPA2 Interrupt Enable

1 = Enable Interrupt on data activity through endpoint A2; 0 = Disable Interrupt on data activity through endpoint A2. Bit 3: EPB0 Interrupt Enable

1 = Enable Interrupt on data activity through endpoint B0; 0 = Disable Interrupt on data activity through endpoint B0 Bit 4: EPB1 Interrupt Enable

1 = Enable Interrupt on data activity through endpoint B1; 0 = Disable Interrupt on data activity through endpoint B1 Bit [7..5] : Reserved

Document #: 38-08002 Rev. *D Page 24 of 49

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