CY7C65113C

Timer LSB

 

 

 

 

 

 

 

Address 0x24

Bit #

7

6

5

4

3

2

1

 

0

Bit Name

Timer Bit 7

TimerBit 6

Timer Bit 5

Timer Bit 4

Timer Bit 3

Timer Bit 2

Timer Bit 1

 

Timer Bit 0

Read/Write

R

R

R

R

R

R

R

 

R

Reset

0

0

0

0

0

0

0

 

0

 

 

 

Figure 10-1. Timer LSB Register

 

 

 

 

Bit [7:0]: Timer lower eight bits.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer MSB

 

 

 

 

 

 

 

Address 0x25

Bit #

7

6

5

4

3

2

1

 

0

Bit Name

Reserved

Reserved

Reserved

Reserved

Timer Bit 11

Timer Bit 10

Timer Bit 9

 

Timer Bit 8

Read/Write

R

R

R

 

R

Reset

0

0

0

0

0

0

0

 

0

Figure 10-2. Timer MSB Register

Bit [3:0]: Timer higher nibble

Bit [7:4]: Reserved.

1.024-ms interrupt 128-s interrupt

11

10 9

8

7

6

5

4

3

2

1

0

1 MHz clock

 

 

 

 

 

 

 

 

 

 

 

 

L3

 

L2

 

L1

L0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D3

 

D2

 

D1

D0

D7

 

 

 

 

 

 

 

 

 

 

 

 

D6 D5 D4 D3 D2 D1 D0

8

Figure 10-3. Timer Block Diagram

To Timer Registers

11.0I2C Configuration Register

Internal hardware supports communication with external devices through an I2C-compatible interface. I2C-compatible function is discussed in detail in Section 12.0.[3] The I2C Position bit (Bit 7, Figure 11-1) and I2C Port Width bit (Bit 1, Figure 11-1) select the locations of the SCL (clock) and SDA (data) pins on Port 1 as shown in Table 11-1. These bits are cleared on reset. When the GPIO is configured for I2C function, the internal pull ups on the pins are disabled. Addition of an external weak pull-up resistors on SCL and SDA is recommended.

.

I2C Configuration

 

 

 

 

 

 

 

 

Address 0x09

 

Bit #

 

7

6

5

4

3

2

1

 

0

 

Bit Name

 

I2C Position

Reserved

Reserved

Reserved

Reserved

Reserved

I2C Port

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

Width

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read/Write

 

R/W

R/W

 

R/W

R/W

R/W

 

R/W

R/W

 

R/W

 

Reset

 

0

0

0

0

0

0

0

 

0

 

 

 

 

 

Figure 11-1. I

2C Configuration Register

 

 

 

 

 

Table 11-1.

I2C Port Configuration

 

 

 

 

 

 

 

 

 

 

I2C Position (Bit7, Figure 11-1)

 

I2C Port Width (Bit1, Figure 11-1)

 

 

I2C Position

 

 

0

 

 

 

0

 

 

I2C on P1[1:0], 0:SCL, 1:SDA

Note:

3.I2C-compatible function must be separately enabled, as described in Section 12.0.

Document #: 38-08002 Rev. *D

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Cypress CY7C65113C manual 11.0 I2C Configuration Register, Timer LSB Address, Timer MSB Address, 2C Configuration Address