CY7C65113C
Document #: 38-08002 Rev. *D Page 4 of 49
Figure 16-5. Hub Ports Force Low Register .........................................................................................31
Figure 16-6. Hub Ports SE0 Status Register .......................................................................................31
Figure 16-7. Hub Ports Data Register ..................................................................................................32
Figure 16-8. Hub Ports Suspend Register ...........................................................................................32
Figure 16-9. Hub Ports Resume Status Register .................................................................................33
Figure 16-10. USB Status and Control Register ..................................................................................33
Figure 17-1. USB Device Address Registers .......................................................................................34
Figure 17-2. USB Device Endpoint Zero Mode Registers ....................................................................35
Figure 17-3. USB Non-control Device Endpoint Mode Registers ........................................................ 36
Figure 17-4. USB Endpoint Counter Registers ....................................................................................36
Figure 17-5. Token/Data Packet Flow Diagram ...................................................................................38
LIST OF TABLES
Table 4-1. Pin Assignments ...................................................................................................................8
Table 4-2. I/O Register Summary ..........................................................................................................9
Table 4-3. Instruction Set Summary .....................................................................................................10
Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity .............................................19
Table 11-1. I2C Port Configuration .......................................................................................................20
Table 12-1. I2C Status and Control Register Bit Definitions .................................................................21
Table 14-1. Interrupt Vector Assignments ............................................................................................26
Table 16-1. Control Bit Definition for Downstream Ports .....................................................................31
Table 16-2. Control Bit Definition for Upstream Port ............................................................................34
Table 17-1. Memory Allocation for Endpoints .....................................................................................35
Table 18-1. USB Register Mode Encoding ..........................................................................................39
Table 18-2. Decode table for Table 18-3: “Details of Modes for Differing Traffic Condition .................40
Table 18-3. Details of Modes for Differing Traffic Conditions ...............................................................41
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