Index, Numerics | Excalibur electronic A-MNL-NIOSPROG-01.1 guide

Numerics

5/16-bit Immediate Value 10

A

About This Manual iii ABS instruction 34 Absolute Value 34 Absolute-Jump Instructions 15 Add Immediate 36

ADD instruction 35 Add Without Carry 35 ADDI instruction 36 Addressing Modes 10 AND instruction 37 ANDN instruction 38 Arithmetic Negation 72 Arithmetic Shift Right 39

Arithmetic Shift Right Immediate 40 ASR instruction 39

ASRI instruction 40

B

BGEN instruction 41 Bit Generate 41 Bitwise Logical AND 37 Bitwise Logical AND NOT 38 Bitwise Logical Exclusive OR 105 Bitwise Logical OR 75

BR instruction 42 Branch 42

branch delay slot 14 Branch Delay Slots 23 branch delay slots 23 Branch To Subroutine 43 BSR instruction 43 Byte-Extract (Dynamic) 49 Byte-Extract (Static) 50 Byte-Fill 52

Index

C

	CALL instruction 44
	Call Subroutine 44
	CLR_IE(%ctl8) 7
	CMP instruction 45
	CMPI instruction 46
	Compare 45
	Compare Immediate 46
	Complex Exception Handlers 22
	Computed Jump 58
	Condition Code Flags 6
	Conditional Instructions 15
	Conditional Instructions 15	3
	Conditionally Execute Next Instruction (IFS) 57	3
	Control Registers 4
	Current Window Pointer (CWP) 5	Index
	D	Index
	D
	Direct CWP Manipulation 24
	Direct Software Exceptions
	(TRAP Instructions) 19
	E
	Equivalent to JMP %i7 (RET) 79
	Equivalent to JMP %o7 62
	Equivalent to MOV %g0, %g0 (NOP) 73
	Equivalent to SKP0 Instruction 54
	Equivalent to SKP1 Instruction (IFO) 53
	Equivalent to SKPRnz Instruction (IFRz) 56
	Equivalent to SKPRz Instruction (IFRnz) 55
	Exception Handling Overview 16
	Exception Processing Sequence 19
	Exception Vector Table 16
	Exceptions 16
	EXT16D instruction 47
	EXT16S instruction 48
	EXT8D instruction 49
	EXT8S instruction 50
	External Hardware Interrupt Sources 17

Altera Corporation

107

Image 119

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Index, Numerics

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision History Information Type Access USA & Canada All Other Locations How to Contact Altera Courier type Typographic ConventionsConventions Visual Cue Meaning Altera Corporation Contents Viii Bit Instruction Set Index 107 Contents Altera Corporation List of Tables Xii Nios CPU Details Bit Nios CPU AudienceNios CPU Architecture Register Groups General-Purpose Registers Clrie Programmer’s Model Control Registers K RegisterProgram Counter Interrrupt Enable IE Condition Code Flags Condition Code Flags Typical 32-bit Nios CPU Program/Data Memory at Address Memory Access OverviewAddress Contents Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing Modes Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate Values Instruction Address Register Data Register Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Partial Width Register-Indirect Offset Range without PFX Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Instruction Address Register Byte/Half-word Index Range Relative-Branch InstructionsInstruction Address Conditional Instructions Absolute-Jump InstructionsTrap Instructions Exception Vector Table Exception Handling Overview Internal Exception Sources External Hardware Interrupt Sources Register Window Overflow Exception Processing Sequence Direct Software Exceptions Trap Instructions Register Window Usage Simple and Complex Exception Handlers Return-Address Pipeline Implementation Pipeline Operation Branch Delay SlotsBR Branch Delay Slot Example Direct CWP Manipulation Notation Meaning Notation Details Instruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1 USR0 Bit Major Opcode Table Sheet 2 MUL Bit Major Opcode Table Sheet 3 Operator Description Operation GNU Compiler/Assembler Pseudo-instructionsPsuedo-Instruction Altera Corporation Bit Instruction Set ABS %r6 ABSAbsolute Value ABS %rA ADD %L3,%g0 ADD %g0 to %L3 ADDAdd Without Carry ADD %rA,%rB Add Immediate Addi PFX %hi16383 Bitwise Logical%rA,%rB PFX %hiconst PFX %hi16384 AndnBitwise Logical and not PFX %hiconst Andn %rA,%loconst Arithmetic Shift Right ASR Arithmetic Shift Right Immediate Asri Bgen %rA,IMM5 Bit Generate BR MainLoop Branch BSR SendCharacter BSRBranch To Subroutine Call Subroutine Call CMP %rA,%rB Compare Cmpi %i3,24 compare %i3 to CmpiCompare Immediate Cmpi & %rA,IMM5 LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16dHalf-Word Extract Dynamic EXT16d %rA,%rB EXT16s %L3,1 %L3 gets upper short int of itself EXT16sHalf-Word Extract Static EXT16s %rA,IMM1 LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8dByte-Extract Dynamic EXT8d %rA,%rB EXT8s %g6,3 %g6 gets the 3rd byte of itself EXT8sByte-Extract Static EXT8s %rA,IMM2 FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL16Half-Word Fill FILL16 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 FILL8Byte-Fill FILL8 %r0,%rA IF0 %rA,IMM5 IF0Equivalent to SKP1 Instruction Equivalent to SKP0 Instruction IF1 IFRnz %rA IFRnz %o3 IFRnzEquivalent to SKPRz Instruction Equivalent to SKPRnz Instruction IFRz Conditionally Execute Next Instruction IFS JMP %o7 return JMPComputed Jump JMP %rA Word offset Load 32-bit Data From Memory LDP %o3,%L2,3 Load %o3 from %L2 + Load 32-bit Data From Memory Pointer Addressing ModeLDP LDS Lret return LretEquivalent to JMP %o7 LSL %L3,%g0 Shift %L3 left by %g0 bits LSLLogical Shift Left LSL %rA,%rB Logical Shift Left Immediate Lsli Logical Shift Right LSR Logical Shift Right Immediate Lsri MOV %o0,%L3 copy %L3 into %o0 MOVRegister-to-Register Move MOV %rA,%rB Movhi %rA,IMM5 MovhiMove Immediate Into High Half-Word Movi %rA,IMM5 MoviMove Immediate Mstep %r1 MstepMultiply-Step Mstep %rA MUL %i5 MultiplyMUL %rA NEG %o4 NEGArithmetic Negation NEG %rA NOP do nothing NOPEquivalent to MOV %g0, %g0 Not %o4 NotLogical Not Not %rA Or %i0,%i1 or %i1 into %i0 Bitwise Logical orOr %rA,%rB PFX %hiconst Or %ra,%loconst PFX 3 affects next instruction PFXPrefix Rdctl %rA RdctlRead Control Register Restore Caller’s Register Window Restore Equivalent to JMP %i7 Restore restores caller’s register windowRET Rotate Left Through Carry RLC Rotate Right Through Carry RRC Save %sp,-IMM8 SaveSave Caller’s Register Window SEXT16 %rA SEXT16Sign Extend 16-bit Value SEXT8 %rA SEXT8Sign Extend 8-bit Value Skip If Register Bit Is SKP0 SKP1 %rA,IMM5 SKP1 Skip If Register Not Equal To SKPRnz SKPRz %rA SKPRz %o3 SKPRzSkip If Register Equals Skps ccIMM4 Skps ccne SkpsSkip On Condition Code Store 32-bit Data To Memory ST16d PFX Y ST16s %rA,%r0,Y 1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address ST16s %rA,%r0,IMM1 FILL8 %r0,%g3 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address ST8d %rA,%r0 Mem%g4 + 36 + ST8sStore 8-bit Data To Memory Static Byte-Offset Address Movi %g4,12 STP Store 32-bit Data To Memory Pointer Addressing Mode STS %sp,IMM8,%rA Store 32-bit Data To Memory Stack Addressing ModeSTS STS16s %sp,IMM9,%r0 Store 16-bit Data To Memory Stack-Addressing ModeSTS16s FILL8 %r0,%rX STS8s %sp,Y,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s STS8s %sp,IMM10,%r0 SUB %rA,%rB SUBSubtract Subi %rB,IMM5 SubiSubtract Immediate Swap Unconditional Trap Trap Trap Return Tret Write Control Register Wrctl XOR %rA,%rB XORBitwise Logical Exclusive or 106 Numerics Index Index Index 110