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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Full Width Register-Indirect

Models: A-MNL-NIOSPROG-01.1

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Overview

Full Width Register-Indirect

The LD and ST instructions can load and store, respectively, a full native- word to or from a register using another register to specify the address. The address is first aligned downward to a native-word aligned address, as described in the “Memory Access Overview” section. The K register is treated as a signed offset, in native words, from the native-word aligned value of the address register.

Table 11. Instructions Using Full Width Register-indirect Addressing

Instruction	Address Register	Data Register

LD	Any	Any

ST	Any	Any

Partial Width Register-Indirect

There are no instructions that read a partial word. To read a partial word, you must combine a full width register-indirect read instruction with an extraction instruction, EXT8d, EXT8s, EXT16d (32-bit Nios CPU only) or EXT16s (32-bit Nios CPU only).

Several instructions can write a partial word. Each of these instructions has a static and a dynamic variant. The position within both the source register and the native-word of memory is determined by the low bits of an addressing register. In the case of a static variant, the position within both the source register and the native-word of memory is determined by a 1- or 2-bit immediate operand to the instruction. As with full width register-indirect addressing, the K register is treated as a signed offset in native words from the native-word aligned value of the address register.

The partial width register-indirect instructions all use %r0 as the source of data to write. These instructions are convenient to use in conjunction with the FILL8 or FILL16 (32-bit Nios CPU only) instructions.

Table 12. Instructions Using Partial Width Register-indirect Addressing

Instruction	Address Register	Data Register	Byte/Half-word Selection

ST8s	Any	%r0	Immediate

ST16s*	Any	%r0	Immediate

ST8d	Any	%r0	Low bits of address register

ST16d*	Any	%r0	Low bits of address register

* 32-bit Nios CPU only

12	Altera Corporation

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Full Width Register-Indirect, Partial Width Register-Indirect

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date DescriptionHow to Contact Altera Information Type Access USA & Canada All Other LocationsTypographic Conventions ConventionsVisual Cue Meaning Courier typeAltera Corporation Contents Bit Instruction Set ViiiContents Index 107Altera Corporation List of Tables Xii Audience Nios CPU ArchitectureNios CPU Details Bit Nios CPU General-Purpose Registers Register GroupsProgrammer’s Model ClrieK Register Program CounterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code FlagsMemory Access Overview Address ContentsTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate ValueInstructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFXInstructions Using Full Width Register-indirect Addressing Full Width Register-IndirectPartial Width Register-Indirect Instruction Address Register Data RegisterFull Width Register-Indirect with Offset Partial Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFXRelative-Branch Instructions Instruction AddressByte/Half-word Index Range Absolute-Jump Instructions Trap InstructionsConditional Instructions Exception Handling Overview Exception Vector TableExternal Hardware Interrupt Sources Internal Exception SourcesRegister Window Overflow Direct Software Exceptions Trap Instructions Exception Processing SequenceRegister Window Usage Return-Address Simple and Complex Exception HandlersPipeline Implementation Branch Delay Slots BR Branch Delay Slot ExamplePipeline Operation Direct CWP Manipulation Notation Details Notation MeaningInstruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format SummaryBit Major Opcode Table Sheet 2 USR0Bit Major Opcode Table Sheet 3 MULGNU Compiler/Assembler Pseudo-instructions Psuedo-InstructionOperator Description Operation Altera Corporation Bit Instruction Set ABS Absolute ValueABS %rA ABS %r6ADD Add Without CarryADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3Addi Add ImmediateBitwise Logical %rA,%rBPFX %hiconst PFX %hi16383Andn Bitwise Logical and notPFX %hiconst Andn %rA,%loconst PFX %hi16384ASR Arithmetic Shift RightAsri Arithmetic Shift Right ImmediateBit Generate Bgen %rA,IMM5Branch BR MainLoopBSR Branch To SubroutineBSR SendCharacter Call Call SubroutineCompare CMP %rA,%rBCmpi Compare ImmediateCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 toEXT16d Half-Word Extract DynamicEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FCEXT16s Half-Word Extract StaticEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itselfEXT8d Byte-Extract DynamicEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FCEXT8s Byte-Extract StaticEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itselfFILL16 Half-Word FillFILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15FILL8 Byte-FillFILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7IF0 Equivalent to SKP1 InstructionIF0 %rA,IMM5 IF1 Equivalent to SKP0 InstructionIFRnz Equivalent to SKPRz InstructionIFRnz %rA IFRnz %o3 IFRz Equivalent to SKPRnz InstructionIFS Conditionally Execute Next InstructionJMP Computed JumpJMP %rA JMP %o7 returnLoad 32-bit Data From Memory Word offsetLoad 32-bit Data From Memory Pointer Addressing Mode LDPLDP %o3,%L2,3 Load %o3 from %L2 + LDS Lret Equivalent to JMP %o7Lret return LSL Logical Shift LeftLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bitsLsli Logical Shift Left ImmediateLSR Logical Shift RightLsri Logical Shift Right ImmediateMOV Register-to-Register MoveMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0Movhi Move Immediate Into High Half-WordMovhi %rA,IMM5 Movi Move ImmediateMovi %rA,IMM5 Mstep Multiply-StepMstep %rA Mstep %r1Multiply MUL %rAMUL %i5 NEG Arithmetic NegationNEG %rA NEG %o4NOP Equivalent to MOV %g0, %g0NOP do nothing Not Logical NotNot %rA Not %o4Bitwise Logical or Or %rA,%rBPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0PFX PrefixPFX 3 affects next instruction Rdctl Read Control RegisterRdctl %rA Restore Restore Caller’s Register WindowRestore restores caller’s register window RETEquivalent to JMP %i7 RLC Rotate Left Through CarryRRC Rotate Right Through CarrySave Save Caller’s Register WindowSave %sp,-IMM8 SEXT16 Sign Extend 16-bit ValueSEXT16 %rA SEXT8 Sign Extend 8-bit ValueSEXT8 %rA SKP0 Skip If Register Bit IsSKP1 SKP1 %rA,IMM5SKPRnz Skip If Register Not Equal ToSKPRz Skip If Register EqualsSKPRz %rA SKPRz %o3 Skps Skip On Condition CodeSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d ST16s Store 16-Bit Data To Memory Static Half-Word-Offset AddressST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1ST8d Store 8-Bit Data To Memory Computed Byte-Pointer AddressST8d %rA,%r0 FILL8 %r0,%g3ST8s Store 8-bit Data To Memory Static Byte-Offset AddressMovi %g4,12 Mem%g4 + 36 +Store 32-bit Data To Memory Pointer Addressing Mode STPStore 32-bit Data To Memory Stack Addressing Mode STSSTS %sp,IMM8,%rA Store 16-bit Data To Memory Stack-Addressing Mode STS16sSTS16s %sp,IMM9,%r0 Store 8-bit Data To Memory Stack-Addressing Mode STS8sSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0SUB SubtractSUB %rA,%rB Subi Subtract ImmediateSubi %rB,IMM5 Swap Trap Unconditional TrapTret Trap ReturnWrctl Write Control RegisterXOR Bitwise Logical Exclusive orXOR %rA,%rB 106 Index NumericsIndex Index 110