Arithmetic Negation

32-Bit Instruction Set

NEG

Operation:					RA ← 0 – RA
Assembler Syntax:					NEG %rA
Example:					NEG %o4
Description:					Negate the value of RA. Perform two’s complement negation of RA.
Condition Codes:					Flags: Unaffected
					N		V	Z	C

					−		−	−	−
Instruction Format:
Instruction Format:					Rw
Instruction Fields:					A = Register index of operand RA
15	14	13	12	11		10		9	8		7	6	5	4	3	2	1	0

0	1	1	1	1		1		0		0	0	0	1			A

72	Altera Corporation

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Image 84

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Arithmetic Negation, NEG %rA, NEG %o4

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date Description How to Contact Altera Information Type Access USA & Canada All Other Locations Typographic Conventions ConventionsVisual Cue Meaning Courier type Altera Corporation Contents Bit Instruction Set Viii Contents Index 107 Altera Corporation List of Tables Xii Audience Nios CPU ArchitectureNios CPU Details Bit Nios CPU General-Purpose Registers Register Groups Programmer’s Model Clrie K Register Program CounterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code Flags Memory Access Overview Address ContentsTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate Value Instructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using Full Width Register-indirect Addressing Full Width Register-IndirectPartial Width Register-Indirect Instruction Address Register Data Register Full Width Register-Indirect with Offset Partial Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFX Relative-Branch Instructions Instruction AddressByte/Half-word Index Range Absolute-Jump Instructions Trap InstructionsConditional Instructions Exception Handling Overview Exception Vector Table External Hardware Interrupt Sources Internal Exception Sources Register Window Overflow Direct Software Exceptions Trap Instructions Exception Processing Sequence Register Window Usage Return-Address Simple and Complex Exception Handlers Pipeline Implementation Branch Delay Slots BR Branch Delay Slot ExamplePipeline Operation Direct CWP Manipulation Notation Details Notation Meaning Instruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 2 USR0 Bit Major Opcode Table Sheet 3 MUL GNU Compiler/Assembler Pseudo-instructions Psuedo-InstructionOperator Description Operation Altera Corporation Bit Instruction Set ABS Absolute ValueABS %rA ABS %r6 ADD Add Without CarryADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3 Addi Add Immediate Bitwise Logical %rA,%rBPFX %hiconst PFX %hi16383 Andn Bitwise Logical and notPFX %hiconst Andn %rA,%loconst PFX %hi16384 ASR Arithmetic Shift Right Asri Arithmetic Shift Right Immediate Bit Generate Bgen %rA,IMM5 Branch BR MainLoop BSR Branch To SubroutineBSR SendCharacter Call Call Subroutine Compare CMP %rA,%rB Cmpi Compare ImmediateCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 to EXT16d Half-Word Extract DynamicEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16s Half-Word Extract StaticEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itself EXT8d Byte-Extract DynamicEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8s Byte-Extract StaticEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itself FILL16 Half-Word FillFILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL8 Byte-FillFILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 IF0 Equivalent to SKP1 InstructionIF0 %rA,IMM5 IF1 Equivalent to SKP0 Instruction IFRnz Equivalent to SKPRz InstructionIFRnz %rA IFRnz %o3 IFRz Equivalent to SKPRnz Instruction IFS Conditionally Execute Next Instruction JMP Computed JumpJMP %rA JMP %o7 return Load 32-bit Data From Memory Word offset Load 32-bit Data From Memory Pointer Addressing Mode LDPLDP %o3,%L2,3 Load %o3 from %L2 + LDS Lret Equivalent to JMP %o7Lret return LSL Logical Shift LeftLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bits Lsli Logical Shift Left Immediate LSR Logical Shift Right Lsri Logical Shift Right Immediate MOV Register-to-Register MoveMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0 Movhi Move Immediate Into High Half-WordMovhi %rA,IMM5 Movi Move ImmediateMovi %rA,IMM5 Mstep Multiply-StepMstep %rA Mstep %r1 Multiply MUL %rAMUL %i5 NEG Arithmetic NegationNEG %rA NEG %o4 NOP Equivalent to MOV %g0, %g0NOP do nothing Not Logical NotNot %rA Not %o4 Bitwise Logical or Or %rA,%rBPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0 PFX PrefixPFX 3 affects next instruction Rdctl Read Control RegisterRdctl %rA Restore Restore Caller’s Register Window Restore restores caller’s register window RETEquivalent to JMP %i7 RLC Rotate Left Through Carry RRC Rotate Right Through Carry Save Save Caller’s Register WindowSave %sp,-IMM8 SEXT16 Sign Extend 16-bit ValueSEXT16 %rA SEXT8 Sign Extend 8-bit ValueSEXT8 %rA SKP0 Skip If Register Bit Is SKP1 SKP1 %rA,IMM5 SKPRnz Skip If Register Not Equal To SKPRz Skip If Register EqualsSKPRz %rA SKPRz %o3 Skps Skip On Condition CodeSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d ST16s Store 16-Bit Data To Memory Static Half-Word-Offset AddressST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1 ST8d Store 8-Bit Data To Memory Computed Byte-Pointer AddressST8d %rA,%r0 FILL8 %r0,%g3 ST8s Store 8-bit Data To Memory Static Byte-Offset AddressMovi %g4,12 Mem%g4 + 36 + Store 32-bit Data To Memory Pointer Addressing Mode STP Store 32-bit Data To Memory Stack Addressing Mode STSSTS %sp,IMM8,%rA Store 16-bit Data To Memory Stack-Addressing Mode STS16sSTS16s %sp,IMM9,%r0 Store 8-bit Data To Memory Stack-Addressing Mode STS8sSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0 SUB SubtractSUB %rA,%rB Subi Subtract ImmediateSubi %rB,IMM5 Swap Trap Unconditional Trap Tret Trap Return Wrctl Write Control Register XOR Bitwise Logical Exclusive orXOR %rA,%rB 106 Index Numerics Index Index 110