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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Byte-Extract Dynamic, EXT8d %rA,%rB

Models: A-MNL-NIOSPROG-01.1

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	32-Bit Instruction Set

	EXT8d
	Byte-Extract (Dynamic)
Operation:	RA ← (0x00.00.00 : bnRA) where n = RB[1..0]
Assembler Syntax:	EXT8d %rA,%rB
Example:	LD %g4,[%i0] ; get 32 bits from [%i0 & 0xFF.FF.FF.FC]
	EXT8d %g4,%i0 ; extract the particular byte at %i0
Description:	Extracts one of the four bytes in RA. The byte to-be-extracted is chosen by bits
	1..0 of RB (byte 3 being the most-significant byte of RA). The selected byte is
	written into bits 7..0 of RA, and the more-significant bits 31..8 are set to zero.

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32-Bit Instruction Set

Condition Codes:						Flags: Unaffected
						N		V		Z		C

						−		−		−		−
Instruction Format:
Instruction Format:						RR
Instruction Fields:						A = Register index of operand RA
						B = Register index of operand RB
15	14	13		12	11		10			9		8		7	6	5	4	3	2	1	0

0	1	0		0	1		1							B					A

Altera Corporation

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Byte-Extract Dynamic, EXT8d %rA,%rB

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision HistoryInformation Type Access USA & Canada All Other Locations How to Contact AlteraConventions Typographic ConventionsVisual Cue Meaning Courier typeAltera Corporation Contents Viii Bit Instruction SetIndex 107 ContentsAltera Corporation List of Tables Xii Nios CPU Architecture AudienceNios CPU Details Bit Nios CPU Register Groups General-Purpose RegistersClrie Programmer’s ModelProgram Counter K RegisterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code FlagsAddress Contents Memory Access OverviewTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing ModesCode Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate ValuesFull Width Register-Indirect Instructions Using Full Width Register-indirect AddressingPartial Width Register-Indirect Instruction Address Register Data RegisterPartial Width Register-Indirect with Offset Full Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFXInstruction Address Relative-Branch InstructionsByte/Half-word Index Range Trap Instructions Absolute-Jump InstructionsConditional Instructions Exception Vector Table Exception Handling OverviewInternal Exception Sources External Hardware Interrupt SourcesRegister Window Overflow Exception Processing Sequence Direct Software Exceptions Trap InstructionsRegister Window Usage Simple and Complex Exception Handlers Return-AddressPipeline Implementation BR Branch Delay Slot Example Branch Delay SlotsPipeline Operation Direct CWP Manipulation Notation Meaning Notation DetailsInstruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1USR0 Bit Major Opcode Table Sheet 2MUL Bit Major Opcode Table Sheet 3Psuedo-Instruction GNU Compiler/Assembler Pseudo-instructionsOperator Description Operation Altera Corporation Bit Instruction Set Absolute Value ABSABS %rA ABS %r6Add Without Carry ADDADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3Add Immediate Addi%rA,%rB Bitwise LogicalPFX %hiconst PFX %hi16383Bitwise Logical and not AndnPFX %hiconst Andn %rA,%loconst PFX %hi16384Arithmetic Shift Right ASRArithmetic Shift Right Immediate AsriBgen %rA,IMM5 Bit GenerateBR MainLoop BranchBranch To Subroutine BSRBSR SendCharacter Call Subroutine CallCMP %rA,%rB CompareCompare Immediate CmpiCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 toHalf-Word Extract Dynamic EXT16dEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FCHalf-Word Extract Static EXT16sEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itselfByte-Extract Dynamic EXT8dEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FCByte-Extract Static EXT8sEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itselfHalf-Word Fill FILL16FILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15Byte-Fill FILL8FILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7Equivalent to SKP1 Instruction IF0IF0 %rA,IMM5 Equivalent to SKP0 Instruction IF1Equivalent to SKPRz Instruction IFRnzIFRnz %rA IFRnz %o3 Equivalent to SKPRnz Instruction IFRzConditionally Execute Next Instruction IFSComputed Jump JMPJMP %rA JMP %o7 returnWord offset Load 32-bit Data From MemoryLDP Load 32-bit Data From Memory Pointer Addressing ModeLDP %o3,%L2,3 Load %o3 from %L2 + LDS Equivalent to JMP %o7 LretLret return Logical Shift Left LSLLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bitsLogical Shift Left Immediate LsliLogical Shift Right LSRLogical Shift Right Immediate LsriRegister-to-Register Move MOVMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0Move Immediate Into High Half-Word MovhiMovhi %rA,IMM5 Move Immediate MoviMovi %rA,IMM5 Multiply-Step MstepMstep %rA Mstep %r1MUL %rA MultiplyMUL %i5 Arithmetic Negation NEGNEG %rA NEG %o4Equivalent to MOV %g0, %g0 NOPNOP do nothing Logical Not NotNot %rA Not %o4Or %rA,%rB Bitwise Logical orPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0Prefix PFXPFX 3 affects next instruction Read Control Register RdctlRdctl %rA Restore Caller’s Register Window RestoreRET Restore restores caller’s register windowEquivalent to JMP %i7 Rotate Left Through Carry RLCRotate Right Through Carry RRCSave Caller’s Register Window SaveSave %sp,-IMM8 Sign Extend 16-bit Value SEXT16SEXT16 %rA Sign Extend 8-bit Value SEXT8SEXT8 %rA Skip If Register Bit Is SKP0SKP1 %rA,IMM5 SKP1Skip If Register Not Equal To SKPRnzSkip If Register Equals SKPRzSKPRz %rA SKPRz %o3 Skip On Condition Code SkpsSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d Store 16-Bit Data To Memory Static Half-Word-Offset Address ST16sST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1Store 8-Bit Data To Memory Computed Byte-Pointer Address ST8dST8d %rA,%r0 FILL8 %r0,%g3Store 8-bit Data To Memory Static Byte-Offset Address ST8sMovi %g4,12 Mem%g4 + 36 +STP Store 32-bit Data To Memory Pointer Addressing ModeSTS Store 32-bit Data To Memory Stack Addressing ModeSTS %sp,IMM8,%rA STS16s Store 16-bit Data To Memory Stack-Addressing ModeSTS16s %sp,IMM9,%r0 STS8s Store 8-bit Data To Memory Stack-Addressing ModeSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0Subtract SUBSUB %rA,%rB Subtract Immediate SubiSubi %rB,IMM5 Swap Unconditional Trap TrapTrap Return TretWrite Control Register WrctlBitwise Logical Exclusive or XORXOR %rA,%rB 106 Numerics IndexIndex Index 110