Bsr, BSR SendCharacter | Excalibur electronic A-MNL-NIOSPROG-01.1

32-Bit Instruction Set

BSR

Branch To Subroutine

Operation:

%o7 ← ((PC + 4) >> 1)

PC ← PC + ((σ(IMM11) + 1) << 1)

Assembler Syntax:

BSR addr

Example:

BSR SendCharacter

NOP ; (delay slot)

Description:

The offset given by IMM11 is interpreted as a signed number of half-words

(instructions) relative to the instruction immediately following BR. Program control

is transferred to instruction at this offset. The return-address is the address of the

BSR instruction plus four, which is the address of the second subsequent

instruction. The return-address is shifted right one bit and stored in %o7. The

right-shifted value stored in %o7 is a destination suitable for direct use by JMP

without modification.

Condition Codes:

Flags: Unaffected

N

V

Z

C

−

−

−

−

Delay Slot Behavior:

The instruction immediately following BSR (BSR’s delay slot) is executed after

BSR, but before the destination instruction. There are restrictions on which

instructions may be used as a delay slot. (Refer to

“Branch Delay Slots” on

page 23)

Instruction Format:

i11

Instruction Fields:

IMM11 = 11-bit immediate value

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

0

0

1

IMM11

2

32-Bit Instruction Set

Altera Corporation

43

Image 55

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Bsr, Branch To Subroutine, BSR SendCharacter

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision History Information Type Access USA & Canada All Other Locations How to Contact Altera Courier type Typographic ConventionsConventions Visual Cue Meaning Altera Corporation Contents Viii Bit Instruction Set Index 107 Contents Altera Corporation List of Tables Xii Nios CPU Architecture AudienceNios CPU Details Bit Nios CPU Register Groups General-Purpose Registers Clrie Programmer’s Model Program Counter K RegisterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code Flags Address Contents Memory Access OverviewTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing Modes Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate Values Instruction Address Register Data Register Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Partial Width Register-Indirect Offset Range without PFX Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Instruction Address Register Instruction Address Relative-Branch InstructionsByte/Half-word Index Range Trap Instructions Absolute-Jump InstructionsConditional Instructions Exception Vector Table Exception Handling Overview Internal Exception Sources External Hardware Interrupt Sources Register Window Overflow Exception Processing Sequence Direct Software Exceptions Trap Instructions Register Window Usage Simple and Complex Exception Handlers Return-Address Pipeline Implementation BR Branch Delay Slot Example Branch Delay SlotsPipeline Operation Direct CWP Manipulation Notation Meaning Notation Details Instruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1 USR0 Bit Major Opcode Table Sheet 2 MUL Bit Major Opcode Table Sheet 3 Psuedo-Instruction GNU Compiler/Assembler Pseudo-instructionsOperator Description Operation Altera Corporation Bit Instruction Set ABS %r6 ABSAbsolute Value ABS %rA ADD %L3,%g0 ADD %g0 to %L3 ADDAdd Without Carry ADD %rA,%rB Add Immediate Addi PFX %hi16383 Bitwise Logical%rA,%rB PFX %hiconst PFX %hi16384 AndnBitwise Logical and not PFX %hiconst Andn %rA,%loconst Arithmetic Shift Right ASR Arithmetic Shift Right Immediate Asri Bgen %rA,IMM5 Bit Generate BR MainLoop Branch Branch To Subroutine BSRBSR SendCharacter Call Subroutine Call CMP %rA,%rB Compare Cmpi %i3,24 compare %i3 to CmpiCompare Immediate Cmpi & %rA,IMM5 LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16dHalf-Word Extract Dynamic EXT16d %rA,%rB EXT16s %L3,1 %L3 gets upper short int of itself EXT16sHalf-Word Extract Static EXT16s %rA,IMM1 LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8dByte-Extract Dynamic EXT8d %rA,%rB EXT8s %g6,3 %g6 gets the 3rd byte of itself EXT8sByte-Extract Static EXT8s %rA,IMM2 FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL16Half-Word Fill FILL16 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 FILL8Byte-Fill FILL8 %r0,%rA Equivalent to SKP1 Instruction IF0IF0 %rA,IMM5 Equivalent to SKP0 Instruction IF1 Equivalent to SKPRz Instruction IFRnzIFRnz %rA IFRnz %o3 Equivalent to SKPRnz Instruction IFRz Conditionally Execute Next Instruction IFS JMP %o7 return JMPComputed Jump JMP %rA Word offset Load 32-bit Data From Memory LDP Load 32-bit Data From Memory Pointer Addressing ModeLDP %o3,%L2,3 Load %o3 from %L2 + LDS Equivalent to JMP %o7 LretLret return LSL %L3,%g0 Shift %L3 left by %g0 bits LSLLogical Shift Left LSL %rA,%rB Logical Shift Left Immediate Lsli Logical Shift Right LSR Logical Shift Right Immediate Lsri MOV %o0,%L3 copy %L3 into %o0 MOVRegister-to-Register Move MOV %rA,%rB Move Immediate Into High Half-Word MovhiMovhi %rA,IMM5 Move Immediate MoviMovi %rA,IMM5 Mstep %r1 MstepMultiply-Step Mstep %rA MUL %rA MultiplyMUL %i5 NEG %o4 NEGArithmetic Negation NEG %rA Equivalent to MOV %g0, %g0 NOPNOP do nothing Not %o4 NotLogical Not Not %rA Or %i0,%i1 or %i1 into %i0 Bitwise Logical orOr %rA,%rB PFX %hiconst Or %ra,%loconst Prefix PFXPFX 3 affects next instruction Read Control Register RdctlRdctl %rA Restore Caller’s Register Window Restore RET Restore restores caller’s register windowEquivalent to JMP %i7 Rotate Left Through Carry RLC Rotate Right Through Carry RRC Save Caller’s Register Window SaveSave %sp,-IMM8 Sign Extend 16-bit Value SEXT16SEXT16 %rA Sign Extend 8-bit Value SEXT8SEXT8 %rA Skip If Register Bit Is SKP0 SKP1 %rA,IMM5 SKP1 Skip If Register Not Equal To SKPRnz Skip If Register Equals SKPRzSKPRz %rA SKPRz %o3 Skip On Condition Code SkpsSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d PFX Y ST16s %rA,%r0,Y 1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address ST16s %rA,%r0,IMM1 FILL8 %r0,%g3 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address ST8d %rA,%r0 Mem%g4 + 36 + ST8sStore 8-bit Data To Memory Static Byte-Offset Address Movi %g4,12 STP Store 32-bit Data To Memory Pointer Addressing Mode STS Store 32-bit Data To Memory Stack Addressing ModeSTS %sp,IMM8,%rA STS16s Store 16-bit Data To Memory Stack-Addressing ModeSTS16s %sp,IMM9,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s STS8s %sp,IMM10,%r0 Subtract SUBSUB %rA,%rB Subtract Immediate SubiSubi %rB,IMM5 Swap Unconditional Trap Trap Trap Return Tret Write Control Register Wrctl Bitwise Logical Exclusive or XORXOR %rA,%rB 106 Numerics Index Index Index 110