Lsr, Logical Shift Right | Excalibur electronic A-MNL-NIOSPROG-01.1

32-Bit Instruction Set

	LSR
	Logical Shift Right
Operation:	RA ← (RA >> RB[4..0]), zero-fill from left
Assembler Syntax:	LSR %rA,%rB
Example:	LSR %L3,%g0 ; Shift %L3 right by %g0 bits
Description:	The value in RA is shifted-right by the number of bits indicated by RB [4..0] (bits
	RB[31..5] are ignored). The result is zero-filled from the left.

Condition Codes:						Flags: Unaffected
						N		V		Z		C

						−		−		−		−
Instruction Format:
Instruction Format:						RR
Instruction Fields:						A = Register index of RA operand
						B = Register index of RB operand
15	14	13		12	11		10			9		8		7	6	5	4	3	2	1	0

0	0	1		0	0		0							B					A

2

32-Bit Instruction Set

Altera Corporation

65

Image 77

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Lsr, Logical Shift Right

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision History Information Type Access USA & Canada All Other Locations How to Contact Altera Conventions Typographic ConventionsVisual Cue Meaning Courier type Altera Corporation Contents Viii Bit Instruction Set Index 107 Contents Altera Corporation List of Tables Xii Nios CPU Details Bit Nios CPU AudienceNios CPU Architecture Register Groups General-Purpose Registers Clrie Programmer’s Model Control Registers K RegisterProgram Counter Interrrupt Enable IE Condition Code Flags Condition Code Flags Typical 32-bit Nios CPU Program/Data Memory at Address Memory Access OverviewAddress Contents Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing Modes Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate Values Full Width Register-Indirect Instructions Using Full Width Register-indirect AddressingPartial Width Register-Indirect Instruction Address Register Data Register Partial Width Register-Indirect with Offset Full Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFX Byte/Half-word Index Range Relative-Branch InstructionsInstruction Address Conditional Instructions Absolute-Jump InstructionsTrap Instructions Exception Vector Table Exception Handling Overview Internal Exception Sources External Hardware Interrupt Sources Register Window Overflow Exception Processing Sequence Direct Software Exceptions Trap Instructions Register Window Usage Simple and Complex Exception Handlers Return-Address Pipeline Implementation Pipeline Operation Branch Delay SlotsBR Branch Delay Slot Example Direct CWP Manipulation Notation Meaning Notation Details Instruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1 USR0 Bit Major Opcode Table Sheet 2 MUL Bit Major Opcode Table Sheet 3 Operator Description Operation GNU Compiler/Assembler Pseudo-instructionsPsuedo-Instruction Altera Corporation Bit Instruction Set Absolute Value ABSABS %rA ABS %r6 Add Without Carry ADDADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3 Add Immediate Addi %rA,%rB Bitwise LogicalPFX %hiconst PFX %hi16383 Bitwise Logical and not AndnPFX %hiconst Andn %rA,%loconst PFX %hi16384 Arithmetic Shift Right ASR Arithmetic Shift Right Immediate Asri Bgen %rA,IMM5 Bit Generate BR MainLoop Branch BSR SendCharacter BSRBranch To Subroutine Call Subroutine Call CMP %rA,%rB Compare Compare Immediate CmpiCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 to Half-Word Extract Dynamic EXT16dEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC Half-Word Extract Static EXT16sEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itself Byte-Extract Dynamic EXT8dEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC Byte-Extract Static EXT8sEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itself Half-Word Fill FILL16FILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 Byte-Fill FILL8FILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 IF0 %rA,IMM5 IF0Equivalent to SKP1 Instruction Equivalent to SKP0 Instruction IF1 IFRnz %rA IFRnz %o3 IFRnzEquivalent to SKPRz Instruction Equivalent to SKPRnz Instruction IFRz Conditionally Execute Next Instruction IFS Computed Jump JMPJMP %rA JMP %o7 return Word offset Load 32-bit Data From Memory LDP %o3,%L2,3 Load %o3 from %L2 + Load 32-bit Data From Memory Pointer Addressing ModeLDP LDS Lret return LretEquivalent to JMP %o7 Logical Shift Left LSLLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bits Logical Shift Left Immediate Lsli Logical Shift Right LSR Logical Shift Right Immediate Lsri Register-to-Register Move MOVMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0 Movhi %rA,IMM5 MovhiMove Immediate Into High Half-Word Movi %rA,IMM5 MoviMove Immediate Multiply-Step MstepMstep %rA Mstep %r1 MUL %i5 MultiplyMUL %rA Arithmetic Negation NEGNEG %rA NEG %o4 NOP do nothing NOPEquivalent to MOV %g0, %g0 Logical Not NotNot %rA Not %o4 Or %rA,%rB Bitwise Logical orPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0 PFX 3 affects next instruction PFXPrefix Rdctl %rA RdctlRead Control Register Restore Caller’s Register Window Restore Equivalent to JMP %i7 Restore restores caller’s register windowRET Rotate Left Through Carry RLC Rotate Right Through Carry RRC Save %sp,-IMM8 SaveSave Caller’s Register Window SEXT16 %rA SEXT16Sign Extend 16-bit Value SEXT8 %rA SEXT8Sign Extend 8-bit Value Skip If Register Bit Is SKP0 SKP1 %rA,IMM5 SKP1 Skip If Register Not Equal To SKPRnz SKPRz %rA SKPRz %o3 SKPRzSkip If Register Equals Skps ccIMM4 Skps ccne SkpsSkip On Condition Code Store 32-bit Data To Memory ST16d Store 16-Bit Data To Memory Static Half-Word-Offset Address ST16sST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1 Store 8-Bit Data To Memory Computed Byte-Pointer Address ST8dST8d %rA,%r0 FILL8 %r0,%g3 Store 8-bit Data To Memory Static Byte-Offset Address ST8sMovi %g4,12 Mem%g4 + 36 + STP Store 32-bit Data To Memory Pointer Addressing Mode STS %sp,IMM8,%rA Store 32-bit Data To Memory Stack Addressing ModeSTS STS16s %sp,IMM9,%r0 Store 16-bit Data To Memory Stack-Addressing ModeSTS16s STS8s Store 8-bit Data To Memory Stack-Addressing ModeSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0 SUB %rA,%rB SUBSubtract Subi %rB,IMM5 SubiSubtract Immediate Swap Unconditional Trap Trap Trap Return Tret Write Control Register Wrctl XOR %rA,%rB XORBitwise Logical Exclusive or 106 Numerics Index Index Index 110