Word offset | Excalibur electronic A-MNL-NIOSPROG-01.1 instruction

32-Bit Instruction Set

LD

Load 32-bit Data From Memory

Operation:

Not preceded by PFX:

RA ← Mem32[align32(RB)]

Preceded by PFX:

RA ← Mem32[align32(RB + σ(K) × 4))]

Assembler Syntax:

LD %rA,[%rB]

Example:

Not preceded by PFX:

LD %g0,[%i3] ; load word at [%i3] into %g0

Preceded by PFX:

PFX 7

; word offset

LD %g0,[%i3] ; load word at [%i3+28] into %g0

Description:

Not preceded by PFX:

Loads a 32-bit data value from memory into RA. Data is always read from a word-

aligned address given by bits 31..2 of RB (the two LSBs of RB are ignored).

Preceded by PFX:

The value in K is sign-extended and used as a word-scaled, signed offset. This

offset is added to the base-address RB (bits 1..0 ignored), and data is read from

the resulting word-aligned address.

Condition Codes:

Flags: Unaffected

N

V

Z

C

−

−

−

−

Instruction Format:

RR

Instruction Fields:

A = Register index of operand RA

B = Register index of operand RB

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

0

1

1

0

B

A

2

32-Bit Instruction Set

Altera Corporation

59

Image 71

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Load 32-bit Data From Memory, Word offset

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision History Information Type Access USA & Canada All Other Locations How to Contact Altera Courier type Typographic ConventionsConventions Visual Cue Meaning Altera Corporation Contents Viii Bit Instruction Set Index 107 Contents Altera Corporation List of Tables Xii Nios CPU Details Bit Nios CPU AudienceNios CPU Architecture Register Groups General-Purpose Registers Clrie Programmer’s Model Control Registers K RegisterProgram Counter Interrrupt Enable IE Condition Code Flags Condition Code Flags Typical 32-bit Nios CPU Program/Data Memory at Address Memory Access OverviewAddress Contents Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing Modes Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate Values Instruction Address Register Data Register Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Partial Width Register-Indirect Offset Range without PFX Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Instruction Address Register Byte/Half-word Index Range Relative-Branch InstructionsInstruction Address Conditional Instructions Absolute-Jump InstructionsTrap Instructions Exception Vector Table Exception Handling Overview Internal Exception Sources External Hardware Interrupt Sources Register Window Overflow Exception Processing Sequence Direct Software Exceptions Trap Instructions Register Window Usage Simple and Complex Exception Handlers Return-Address Pipeline Implementation Pipeline Operation Branch Delay SlotsBR Branch Delay Slot Example Direct CWP Manipulation Notation Meaning Notation Details Instruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1 USR0 Bit Major Opcode Table Sheet 2 MUL Bit Major Opcode Table Sheet 3 Operator Description Operation GNU Compiler/Assembler Pseudo-instructionsPsuedo-Instruction Altera Corporation Bit Instruction Set ABS %r6 ABSAbsolute Value ABS %rA ADD %L3,%g0 ADD %g0 to %L3 ADDAdd Without Carry ADD %rA,%rB Add Immediate Addi PFX %hi16383 Bitwise Logical%rA,%rB PFX %hiconst PFX %hi16384 AndnBitwise Logical and not PFX %hiconst Andn %rA,%loconst Arithmetic Shift Right ASR Arithmetic Shift Right Immediate Asri Bgen %rA,IMM5 Bit Generate BR MainLoop Branch BSR SendCharacter BSRBranch To Subroutine Call Subroutine Call CMP %rA,%rB Compare Cmpi %i3,24 compare %i3 to CmpiCompare Immediate Cmpi & %rA,IMM5 LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16dHalf-Word Extract Dynamic EXT16d %rA,%rB EXT16s %L3,1 %L3 gets upper short int of itself EXT16sHalf-Word Extract Static EXT16s %rA,IMM1 LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8dByte-Extract Dynamic EXT8d %rA,%rB EXT8s %g6,3 %g6 gets the 3rd byte of itself EXT8sByte-Extract Static EXT8s %rA,IMM2 FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL16Half-Word Fill FILL16 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 FILL8Byte-Fill FILL8 %r0,%rA IF0 %rA,IMM5 IF0Equivalent to SKP1 Instruction Equivalent to SKP0 Instruction IF1 IFRnz %rA IFRnz %o3 IFRnzEquivalent to SKPRz Instruction Equivalent to SKPRnz Instruction IFRz Conditionally Execute Next Instruction IFS JMP %o7 return JMPComputed Jump JMP %rA Word offset Load 32-bit Data From Memory LDP %o3,%L2,3 Load %o3 from %L2 + Load 32-bit Data From Memory Pointer Addressing ModeLDP LDS Lret return LretEquivalent to JMP %o7 LSL %L3,%g0 Shift %L3 left by %g0 bits LSLLogical Shift Left LSL %rA,%rB Logical Shift Left Immediate Lsli Logical Shift Right LSR Logical Shift Right Immediate Lsri MOV %o0,%L3 copy %L3 into %o0 MOVRegister-to-Register Move MOV %rA,%rB Movhi %rA,IMM5 MovhiMove Immediate Into High Half-Word Movi %rA,IMM5 MoviMove Immediate Mstep %r1 MstepMultiply-Step Mstep %rA MUL %i5 MultiplyMUL %rA NEG %o4 NEGArithmetic Negation NEG %rA NOP do nothing NOPEquivalent to MOV %g0, %g0 Not %o4 NotLogical Not Not %rA Or %i0,%i1 or %i1 into %i0 Bitwise Logical orOr %rA,%rB PFX %hiconst Or %ra,%loconst PFX 3 affects next instruction PFXPrefix Rdctl %rA RdctlRead Control Register Restore Caller’s Register Window Restore Equivalent to JMP %i7 Restore restores caller’s register windowRET Rotate Left Through Carry RLC Rotate Right Through Carry RRC Save %sp,-IMM8 SaveSave Caller’s Register Window SEXT16 %rA SEXT16Sign Extend 16-bit Value SEXT8 %rA SEXT8Sign Extend 8-bit Value Skip If Register Bit Is SKP0 SKP1 %rA,IMM5 SKP1 Skip If Register Not Equal To SKPRnz SKPRz %rA SKPRz %o3 SKPRzSkip If Register Equals Skps ccIMM4 Skps ccne SkpsSkip On Condition Code Store 32-bit Data To Memory ST16d PFX Y ST16s %rA,%r0,Y 1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address ST16s %rA,%r0,IMM1 FILL8 %r0,%g3 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address ST8d %rA,%r0 Mem%g4 + 36 + ST8sStore 8-bit Data To Memory Static Byte-Offset Address Movi %g4,12 STP Store 32-bit Data To Memory Pointer Addressing Mode STS %sp,IMM8,%rA Store 32-bit Data To Memory Stack Addressing ModeSTS STS16s %sp,IMM9,%r0 Store 16-bit Data To Memory Stack-Addressing ModeSTS16s FILL8 %r0,%rX STS8s %sp,Y,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s STS8s %sp,IMM10,%r0 SUB %rA,%rB SUBSubtract Subi %rB,IMM5 SubiSubtract Immediate Swap Unconditional Trap Trap Trap Return Tret Write Control Register Wrctl XOR %rA,%rB XORBitwise Logical Exclusive or 106 Numerics Index Index Index 110