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Excalibur electronic A-MNL-NIOSPROG-01.1 manual IFRz, Equivalent to SKPRnz Instruction

Models: A-MNL-NIOSPROG-01.1

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32-Bit Instruction Set

IFRz

Equivalent to SKPRnz Instruction

Operation:

Assembler Syntax: Example:

if (RA ! = 0) then begin

if (Mem16[PC + 2] is PFX) then PC ← PC + 6

else PC ← PC + 4

end

IFRz %rA

IFRz %g3

BSR SendIt ; only call if %g3 is zero

NOP ; (delay slot) executed in either case

Description:					Skip next instruction if RA is not zero. If the next instruction is PFX, then both PFX
					and the instruction following PFX are skipped together.
Condition Codes:					Flags: Unaffected
					N		V	Z	C

					−		−	−	−
Instruction Format:					Rw
Instruction Fields:					A = Register index of operand RA
15	14	13	12	11		10		9	8		7	6	5	4	3	2	1	0

0	1	1	1	1		1		1		1	0	1	0			A

56	Altera Corporation

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual IFRz, Equivalent to SKPRnz Instruction

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date DescriptionHow to Contact Altera Information Type Access USA & Canada All Other LocationsTypographic Conventions ConventionsVisual Cue Meaning Courier typeAltera Corporation Contents Bit Instruction Set ViiiContents Index 107Altera Corporation List of Tables Xii Nios CPU Details Bit Nios CPU AudienceNios CPU Architecture General-Purpose Registers Register GroupsProgrammer’s Model ClrieControl Registers K RegisterProgram Counter Interrrupt Enable IE Condition Code Flags Condition Code FlagsTypical 32-bit Nios CPU Program/Data Memory at Address Memory Access OverviewAddress Contents Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate ValueInstructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFXInstructions Using Full Width Register-indirect Addressing Full Width Register-IndirectPartial Width Register-Indirect Instruction Address Register Data RegisterFull Width Register-Indirect with Offset Partial Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFXByte/Half-word Index Range Relative-Branch InstructionsInstruction Address Conditional Instructions Absolute-Jump InstructionsTrap Instructions Exception Handling Overview Exception Vector TableExternal Hardware Interrupt Sources Internal Exception SourcesRegister Window Overflow Direct Software Exceptions Trap Instructions Exception Processing SequenceRegister Window Usage Return-Address Simple and Complex Exception HandlersPipeline Implementation Pipeline Operation Branch Delay SlotsBR Branch Delay Slot Example Direct CWP Manipulation Notation Details Notation MeaningInstruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format SummaryBit Major Opcode Table Sheet 2 USR0Bit Major Opcode Table Sheet 3 MULOperator Description Operation GNU Compiler/Assembler Pseudo-instructionsPsuedo-Instruction Altera Corporation Bit Instruction Set ABS Absolute ValueABS %rA ABS %r6ADD Add Without CarryADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3Addi Add ImmediateBitwise Logical %rA,%rBPFX %hiconst PFX %hi16383Andn Bitwise Logical and notPFX %hiconst Andn %rA,%loconst PFX %hi16384ASR Arithmetic Shift RightAsri Arithmetic Shift Right ImmediateBit Generate Bgen %rA,IMM5Branch BR MainLoopBSR SendCharacter BSRBranch To Subroutine Call Call SubroutineCompare CMP %rA,%rBCmpi Compare ImmediateCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 toEXT16d Half-Word Extract DynamicEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FCEXT16s Half-Word Extract StaticEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itselfEXT8d Byte-Extract DynamicEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FCEXT8s Byte-Extract StaticEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itselfFILL16 Half-Word FillFILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15FILL8 Byte-FillFILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7IF0 %rA,IMM5 IF0Equivalent to SKP1 Instruction IF1 Equivalent to SKP0 InstructionIFRnz %rA IFRnz %o3 IFRnzEquivalent to SKPRz Instruction IFRz Equivalent to SKPRnz InstructionIFS Conditionally Execute Next InstructionJMP Computed JumpJMP %rA JMP %o7 returnLoad 32-bit Data From Memory Word offsetLDP %o3,%L2,3 Load %o3 from %L2 + Load 32-bit Data From Memory Pointer Addressing ModeLDP LDS Lret return LretEquivalent to JMP %o7 LSL Logical Shift LeftLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bitsLsli Logical Shift Left ImmediateLSR Logical Shift RightLsri Logical Shift Right ImmediateMOV Register-to-Register MoveMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0Movhi %rA,IMM5 MovhiMove Immediate Into High Half-Word Movi %rA,IMM5 MoviMove Immediate Mstep Multiply-StepMstep %rA Mstep %r1MUL %i5 MultiplyMUL %rA NEG Arithmetic NegationNEG %rA NEG %o4NOP do nothing NOPEquivalent to MOV %g0, %g0 Not Logical NotNot %rA Not %o4Bitwise Logical or Or %rA,%rBPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0PFX 3 affects next instruction PFXPrefix Rdctl %rA RdctlRead Control Register Restore Restore Caller’s Register WindowEquivalent to JMP %i7 Restore restores caller’s register windowRET RLC Rotate Left Through CarryRRC Rotate Right Through CarrySave %sp,-IMM8 SaveSave Caller’s Register Window SEXT16 %rA SEXT16Sign Extend 16-bit Value SEXT8 %rA SEXT8Sign Extend 8-bit Value SKP0 Skip If Register Bit IsSKP1 SKP1 %rA,IMM5SKPRnz Skip If Register Not Equal ToSKPRz %rA SKPRz %o3 SKPRzSkip If Register Equals Skps ccIMM4 Skps ccne SkpsSkip On Condition Code Store 32-bit Data To Memory ST16d ST16s Store 16-Bit Data To Memory Static Half-Word-Offset AddressST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1ST8d Store 8-Bit Data To Memory Computed Byte-Pointer AddressST8d %rA,%r0 FILL8 %r0,%g3ST8s Store 8-bit Data To Memory Static Byte-Offset AddressMovi %g4,12 Mem%g4 + 36 +Store 32-bit Data To Memory Pointer Addressing Mode STPSTS %sp,IMM8,%rA Store 32-bit Data To Memory Stack Addressing ModeSTS STS16s %sp,IMM9,%r0 Store 16-bit Data To Memory Stack-Addressing ModeSTS16s Store 8-bit Data To Memory Stack-Addressing Mode STS8sSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0SUB %rA,%rB SUBSubtract Subi %rB,IMM5 SubiSubtract Immediate Swap Trap Unconditional TrapTret Trap ReturnWrctl Write Control RegisterXOR %rA,%rB XORBitwise Logical Exclusive or 106 Index NumericsIndex Index 110