Mul | Excalibur electronic A-MNL-NIOSPROG-01.1 specification

Overview

Table 17. 32-bit Major Opcode Table (Sheet 3 of 3)

Opcode	Mnemonic	Format	Summary

01111101111

01111110000	ST8d	Rw	bnMem32 [align32(RA +(σ(K) × 4))] ← bn%r0
			where n = RA[1..0]

01111110001	ST16d	Rw	hnMem32 [align32(RA + (σ(K) × 4))] ← hn%r0
			where n = RA[1]

01111110010	FILL8	Rw	%r0 ← (b0RA : b0RA : b0RA : b0RA)
01111110011	FILL16	Rw	%r0 ← (h0RA : h0RA)
01111110100	MSTEP	Rw	if (%r0[31] == 1) then %r0 ← (%r0 << 1) + RA else %r0
			← (%r0 << 1)
01111110101	MUL	Rw	%r0 ← (%r0 & 0x0000.ffff) × (RA & 0x0000.ffff)
01111110110	SKPRz	Rw	Skip next instruction if:(RA ==0)

01111110111	SKPS	i4w	Skip next instruction if condition encoded by IMM4w is true

01111111000	WRCTL	Rw	CTLk ← RA
01111111001	RDCTL	Rw	RA ← CTLk
01111111010	SKPRnz	Rw	Skip next instruction if: (RA ! = 0)

01111111011

01111111100

01111111101

01111111110	JMP	Rw	PC ← (RA × 2)
01111111111	CALL	Rw	R15 ←((PC + 4) >> 1); PC ← (RA × 2)
100000	BR	i11	PC ← PC + ((σ(IMM11) + 1) × 2)
100001

100010	BSR	i11	PC ← PC + ((σ(IMM11) + 1) × 2);
			%r15 ← ((PC + 4) >> 1)

10011	PFX	i11	K ← IMM11 (K set to zero after next instruction)
1010	STP	RPi5	Mem32[align32(RP + (σ(K : IMM5) × 4))] ← RA

1011	LDP	RPi5	RA ← Mem32 [align32(RP + (σ(K : IMM5) × 4))]

110	STS	Ri8	Mem32[align32(%sp + (IMM8 × 4) )] ← RA
111	LDS	Ri8	RA ← Mem32 [align32(%sp + (IMM8 × 4))]

30	Altera Corporation

Image 42

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Bit Major Opcode Table Sheet 3, Mul

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date Description How to Contact Altera Information Type Access USA & Canada All Other Locations Visual Cue Meaning Typographic ConventionsConventions Courier type Altera Corporation Contents Bit Instruction Set Viii Contents Index 107 Altera Corporation List of Tables Xii Audience Nios CPU ArchitectureNios CPU Details Bit Nios CPU General-Purpose Registers Register Groups Programmer’s Model Clrie K Register Program CounterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code Flags Memory Access Overview Address ContentsTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate Value Instructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFX Partial Width Register-Indirect Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Instruction Address Register Data Register Instruction Address Register Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Offset Range without PFX Relative-Branch Instructions Instruction AddressByte/Half-word Index Range Absolute-Jump Instructions Trap InstructionsConditional Instructions Exception Handling Overview Exception Vector Table External Hardware Interrupt Sources Internal Exception Sources Register Window Overflow Direct Software Exceptions Trap Instructions Exception Processing Sequence Register Window Usage Return-Address Simple and Complex Exception Handlers Pipeline Implementation Branch Delay Slots BR Branch Delay Slot ExamplePipeline Operation Direct CWP Manipulation Notation Details Notation Meaning Instruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 2 USR0 Bit Major Opcode Table Sheet 3 MUL GNU Compiler/Assembler Pseudo-instructions Psuedo-InstructionOperator Description Operation Altera Corporation Bit Instruction Set ABS %rA ABSAbsolute Value ABS %r6 ADD %rA,%rB ADDAdd Without Carry ADD %L3,%g0 ADD %g0 to %L3 Addi Add Immediate PFX %hiconst Bitwise Logical%rA,%rB PFX %hi16383 PFX %hiconst Andn %rA,%loconst AndnBitwise Logical and not PFX %hi16384 ASR Arithmetic Shift Right Asri Arithmetic Shift Right Immediate Bit Generate Bgen %rA,IMM5 Branch BR MainLoop BSR Branch To SubroutineBSR SendCharacter Call Call Subroutine Compare CMP %rA,%rB Cmpi & %rA,IMM5 CmpiCompare Immediate Cmpi %i3,24 compare %i3 to EXT16d %rA,%rB EXT16dHalf-Word Extract Dynamic LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16s %rA,IMM1 EXT16sHalf-Word Extract Static EXT16s %L3,1 %L3 gets upper short int of itself EXT8d %rA,%rB EXT8dByte-Extract Dynamic LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8s %rA,IMM2 EXT8sByte-Extract Static EXT8s %g6,3 %g6 gets the 3rd byte of itself FILL16 %r0,%rA FILL16Half-Word Fill FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL8 %r0,%rA FILL8Byte-Fill FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 IF0 Equivalent to SKP1 InstructionIF0 %rA,IMM5 IF1 Equivalent to SKP0 Instruction IFRnz Equivalent to SKPRz InstructionIFRnz %rA IFRnz %o3 IFRz Equivalent to SKPRnz Instruction IFS Conditionally Execute Next Instruction JMP %rA JMPComputed Jump JMP %o7 return Load 32-bit Data From Memory Word offset Load 32-bit Data From Memory Pointer Addressing Mode LDPLDP %o3,%L2,3 Load %o3 from %L2 + LDS Lret Equivalent to JMP %o7Lret return LSL %rA,%rB LSLLogical Shift Left LSL %L3,%g0 Shift %L3 left by %g0 bits Lsli Logical Shift Left Immediate LSR Logical Shift Right Lsri Logical Shift Right Immediate MOV %rA,%rB MOVRegister-to-Register Move MOV %o0,%L3 copy %L3 into %o0 Movhi Move Immediate Into High Half-WordMovhi %rA,IMM5 Movi Move ImmediateMovi %rA,IMM5 Mstep %rA MstepMultiply-Step Mstep %r1 Multiply MUL %rAMUL %i5 NEG %rA NEGArithmetic Negation NEG %o4 NOP Equivalent to MOV %g0, %g0NOP do nothing Not %rA NotLogical Not Not %o4 PFX %hiconst Or %ra,%loconst Bitwise Logical orOr %rA,%rB Or %i0,%i1 or %i1 into %i0 PFX PrefixPFX 3 affects next instruction Rdctl Read Control RegisterRdctl %rA Restore Restore Caller’s Register Window Restore restores caller’s register window RETEquivalent to JMP %i7 RLC Rotate Left Through Carry RRC Rotate Right Through Carry Save Save Caller’s Register WindowSave %sp,-IMM8 SEXT16 Sign Extend 16-bit ValueSEXT16 %rA SEXT8 Sign Extend 8-bit ValueSEXT8 %rA SKP0 Skip If Register Bit Is SKP1 SKP1 %rA,IMM5 SKPRnz Skip If Register Not Equal To SKPRz Skip If Register EqualsSKPRz %rA SKPRz %o3 Skps Skip On Condition CodeSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d ST16s %rA,%r0,IMM1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address PFX Y ST16s %rA,%r0,Y 1 ST8d %rA,%r0 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address FILL8 %r0,%g3 Movi %g4,12 ST8sStore 8-bit Data To Memory Static Byte-Offset Address Mem%g4 + 36 + Store 32-bit Data To Memory Pointer Addressing Mode STP Store 32-bit Data To Memory Stack Addressing Mode STSSTS %sp,IMM8,%rA Store 16-bit Data To Memory Stack-Addressing Mode STS16sSTS16s %sp,IMM9,%r0 STS8s %sp,IMM10,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s FILL8 %r0,%rX STS8s %sp,Y,%r0 SUB SubtractSUB %rA,%rB Subi Subtract ImmediateSubi %rB,IMM5 Swap Trap Unconditional Trap Tret Trap Return Wrctl Write Control Register XOR Bitwise Logical Exclusive orXOR %rA,%rB 106 Index Numerics Index Index 110