Addressing Modes | Excalibur electronic A-MNL-NIOSPROG-01.1 specification

Overview

Code Example 2 shows how to write a single byte to memory, even if the address of the byte is not native-word-aligned.

Code Example 2: Single Byte Written to Memory—Address is not Native-word-aligned

Instructions executed on a 32-bit Nios CPU

;Let’s assume %o4 contains the address 0x00001203

;and that %g3 contains the value 0x00000054

FILL8 %r0,%g3 ; (First operand can only be %r0)

;replicate low byte of %g3 across %r0

;so %r0 contains 0x54545454

ST8d [%o4],%r0 ; (Second operand can only be %r0)

; Stores the 3rd byte of %r0 to address 0x1203

Contents of memory after:

0 1 2 3

0x00001200 0x46 0x49 0x53 0x54

Addressing Modes

The topics in this section includes a description of the following addressing modes:

■5/16-bit immediate

■Full width register-indirect

■Partial width register-indirect

■Full width register-indirect with offset

■Partial width register-indirect with offset

5/16-bit Immediate Value

Many arithmetic and logical instructions take a 5-bit immediate value as an operand. The ADDI instruction, for example, has two operands: a register and a 5-bit immediate value. A 5-bit immediate value represents a constant from 0 to 31. To specify a constant value that requires from 6 to 16 bits (a number from 32 to 65535), the 11-bit K register can be set using the PFX instruction, This value is concatenated with the 5-bit immediate value. The PFX instruction must be used directly before the instruction it modifies.

To support breaking 16-bit immediate constants into a PFX value and a 5-bit immediate value, the assembler provides the operators %hi() and %lo(). %hi(x) extracts the 11 bits from bit 5 to bit 15 from constant x, and %lo(x) extracts the 5 bits from bit 0 to bit 4 from constant x.

10	Altera Corporation

Image 22

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Addressing Modes, Bit Immediate Value

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date Description How to Contact Altera Information Type Access USA & Canada All Other Locations Visual Cue Meaning Typographic ConventionsConventions Courier type Altera Corporation Contents Bit Instruction Set Viii Contents Index 107 Altera Corporation List of Tables Xii Nios CPU Architecture AudienceNios CPU Details Bit Nios CPU General-Purpose Registers Register Groups Programmer’s Model Clrie Program Counter K RegisterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code Flags Address Contents Memory Access OverviewTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate Value Instructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFX Partial Width Register-Indirect Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Instruction Address Register Data Register Instruction Address Register Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Offset Range without PFX Instruction Address Relative-Branch InstructionsByte/Half-word Index Range Trap Instructions Absolute-Jump InstructionsConditional Instructions Exception Handling Overview Exception Vector Table External Hardware Interrupt Sources Internal Exception Sources Register Window Overflow Direct Software Exceptions Trap Instructions Exception Processing Sequence Register Window Usage Return-Address Simple and Complex Exception Handlers Pipeline Implementation BR Branch Delay Slot Example Branch Delay SlotsPipeline Operation Direct CWP Manipulation Notation Details Notation Meaning Instruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 2 USR0 Bit Major Opcode Table Sheet 3 MUL Psuedo-Instruction GNU Compiler/Assembler Pseudo-instructionsOperator Description Operation Altera Corporation Bit Instruction Set ABS %rA ABSAbsolute Value ABS %r6 ADD %rA,%rB ADDAdd Without Carry ADD %L3,%g0 ADD %g0 to %L3 Addi Add Immediate PFX %hiconst Bitwise Logical%rA,%rB PFX %hi16383 PFX %hiconst Andn %rA,%loconst AndnBitwise Logical and not PFX %hi16384 ASR Arithmetic Shift Right Asri Arithmetic Shift Right Immediate Bit Generate Bgen %rA,IMM5 Branch BR MainLoop Branch To Subroutine BSRBSR SendCharacter Call Call Subroutine Compare CMP %rA,%rB Cmpi & %rA,IMM5 CmpiCompare Immediate Cmpi %i3,24 compare %i3 to EXT16d %rA,%rB EXT16dHalf-Word Extract Dynamic LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16s %rA,IMM1 EXT16sHalf-Word Extract Static EXT16s %L3,1 %L3 gets upper short int of itself EXT8d %rA,%rB EXT8dByte-Extract Dynamic LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8s %rA,IMM2 EXT8sByte-Extract Static EXT8s %g6,3 %g6 gets the 3rd byte of itself FILL16 %r0,%rA FILL16Half-Word Fill FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL8 %r0,%rA FILL8Byte-Fill FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 Equivalent to SKP1 Instruction IF0IF0 %rA,IMM5 IF1 Equivalent to SKP0 Instruction Equivalent to SKPRz Instruction IFRnzIFRnz %rA IFRnz %o3 IFRz Equivalent to SKPRnz Instruction IFS Conditionally Execute Next Instruction JMP %rA JMPComputed Jump JMP %o7 return Load 32-bit Data From Memory Word offset LDP Load 32-bit Data From Memory Pointer Addressing ModeLDP %o3,%L2,3 Load %o3 from %L2 + LDS Equivalent to JMP %o7 LretLret return LSL %rA,%rB LSLLogical Shift Left LSL %L3,%g0 Shift %L3 left by %g0 bits Lsli Logical Shift Left Immediate LSR Logical Shift Right Lsri Logical Shift Right Immediate MOV %rA,%rB MOVRegister-to-Register Move MOV %o0,%L3 copy %L3 into %o0 Move Immediate Into High Half-Word MovhiMovhi %rA,IMM5 Move Immediate MoviMovi %rA,IMM5 Mstep %rA MstepMultiply-Step Mstep %r1 MUL %rA MultiplyMUL %i5 NEG %rA NEGArithmetic Negation NEG %o4 Equivalent to MOV %g0, %g0 NOPNOP do nothing Not %rA NotLogical Not Not %o4 PFX %hiconst Or %ra,%loconst Bitwise Logical orOr %rA,%rB Or %i0,%i1 or %i1 into %i0 Prefix PFXPFX 3 affects next instruction Read Control Register RdctlRdctl %rA Restore Restore Caller’s Register Window RET Restore restores caller’s register windowEquivalent to JMP %i7 RLC Rotate Left Through Carry RRC Rotate Right Through Carry Save Caller’s Register Window SaveSave %sp,-IMM8 Sign Extend 16-bit Value SEXT16SEXT16 %rA Sign Extend 8-bit Value SEXT8SEXT8 %rA SKP0 Skip If Register Bit Is SKP1 SKP1 %rA,IMM5 SKPRnz Skip If Register Not Equal To Skip If Register Equals SKPRzSKPRz %rA SKPRz %o3 Skip On Condition Code SkpsSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d ST16s %rA,%r0,IMM1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address PFX Y ST16s %rA,%r0,Y 1 ST8d %rA,%r0 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address FILL8 %r0,%g3 Movi %g4,12 ST8sStore 8-bit Data To Memory Static Byte-Offset Address Mem%g4 + 36 + Store 32-bit Data To Memory Pointer Addressing Mode STP STS Store 32-bit Data To Memory Stack Addressing ModeSTS %sp,IMM8,%rA STS16s Store 16-bit Data To Memory Stack-Addressing ModeSTS16s %sp,IMM9,%r0 STS8s %sp,IMM10,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s FILL8 %r0,%rX STS8s %sp,Y,%r0 Subtract SUBSUB %rA,%rB Subtract Immediate SubiSubi %rB,IMM5 Swap Trap Unconditional Trap Tret Trap Return Wrctl Write Control Register Bitwise Logical Exclusive or XORXOR %rA,%rB 106 Index Numerics Index Index 110