Offset Range without PFX | Excalibur electronic A-MNL-NIOSPROG-01.1

Overview

Full Width Register-Indirect with Offset

The LDP, LDS, STP and STS instructions can load or store a full native- word to or from a register using another register to specify an address, and an immediate value to specify an offset, in native words, from that address.

Unlike the LD and ST instructions, which can use any register to specify a memory address, these instructions may each only use particular registers for their address. The LDP and STP instructions may each only use the register %L0, %L1, %L2, or %L3 for their address registers. The LDS and STS instructions may only use the stack pointer, register %sp (equivalent to %o6), as their address register. These instructions each take a signed immediate index value that specifies an offset in native words from the aligned address pointed in the address register.

Table 13. Instructions Using Full Width Register-indirect with Offset Addressing

Instruction	Address Register		Data Register	Offset Range without PFX

LDP	%L0,	%L1, %L2, %L3	Any	-16..15 native-words

LDS		%sp	Any	0..255 native-words

STP	%L0,	%L1, %L2, %L3	Any	-16..15 native-words

STS		%sp	Any	0..255 native-words

Partial Width Register-Indirect with Offset

There are no instructions that read a partial word from memory. To read a partial word, you must combine a full width indexed register-indirect read instruction with an extraction instruction, EXT8d, EXT8s, EXT16d (32-bit Nios CPU only) or EXT16s (32-bit Nios CPU only). The STS8s and STS16s (Nios 32 only) use an immediate constant to specify a byte or half- word offset, respectively, from the stack pointer to write the correspondingly aligned partial width of the source register %r0.

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Overview

Altera Corporation

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Full Width Register-Indirect with Offset, Instruction Address Register

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision History Information Type Access USA & Canada All Other Locations How to Contact Altera Conventions Typographic ConventionsVisual Cue Meaning Courier type Altera Corporation Contents Viii Bit Instruction Set Index 107 Contents Altera Corporation List of Tables Xii Nios CPU Architecture AudienceNios CPU Details Bit Nios CPU Register Groups General-Purpose Registers Clrie Programmer’s Model Program Counter K RegisterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code Flags Address Contents Memory Access OverviewTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing Modes Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate Values Full Width Register-Indirect Instructions Using Full Width Register-indirect AddressingPartial Width Register-Indirect Instruction Address Register Data Register Partial Width Register-Indirect with Offset Full Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFX Instruction Address Relative-Branch InstructionsByte/Half-word Index Range Trap Instructions Absolute-Jump InstructionsConditional Instructions Exception Vector Table Exception Handling Overview Internal Exception Sources External Hardware Interrupt Sources Register Window Overflow Exception Processing Sequence Direct Software Exceptions Trap Instructions Register Window Usage Simple and Complex Exception Handlers Return-Address Pipeline Implementation BR Branch Delay Slot Example Branch Delay SlotsPipeline Operation Direct CWP Manipulation Notation Meaning Notation Details Instruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1 USR0 Bit Major Opcode Table Sheet 2 MUL Bit Major Opcode Table Sheet 3 Psuedo-Instruction GNU Compiler/Assembler Pseudo-instructionsOperator Description Operation Altera Corporation Bit Instruction Set Absolute Value ABSABS %rA ABS %r6 Add Without Carry ADDADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3 Add Immediate Addi %rA,%rB Bitwise LogicalPFX %hiconst PFX %hi16383 Bitwise Logical and not AndnPFX %hiconst Andn %rA,%loconst PFX %hi16384 Arithmetic Shift Right ASR Arithmetic Shift Right Immediate Asri Bgen %rA,IMM5 Bit Generate BR MainLoop Branch Branch To Subroutine BSRBSR SendCharacter Call Subroutine Call CMP %rA,%rB Compare Compare Immediate CmpiCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 to Half-Word Extract Dynamic EXT16dEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC Half-Word Extract Static EXT16sEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itself Byte-Extract Dynamic EXT8dEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC Byte-Extract Static EXT8sEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itself Half-Word Fill FILL16FILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 Byte-Fill FILL8FILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 Equivalent to SKP1 Instruction IF0IF0 %rA,IMM5 Equivalent to SKP0 Instruction IF1 Equivalent to SKPRz Instruction IFRnzIFRnz %rA IFRnz %o3 Equivalent to SKPRnz Instruction IFRz Conditionally Execute Next Instruction IFS Computed Jump JMPJMP %rA JMP %o7 return Word offset Load 32-bit Data From Memory LDP Load 32-bit Data From Memory Pointer Addressing ModeLDP %o3,%L2,3 Load %o3 from %L2 + LDS Equivalent to JMP %o7 LretLret return Logical Shift Left LSLLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bits Logical Shift Left Immediate Lsli Logical Shift Right LSR Logical Shift Right Immediate Lsri Register-to-Register Move MOVMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0 Move Immediate Into High Half-Word MovhiMovhi %rA,IMM5 Move Immediate MoviMovi %rA,IMM5 Multiply-Step MstepMstep %rA Mstep %r1 MUL %rA MultiplyMUL %i5 Arithmetic Negation NEGNEG %rA NEG %o4 Equivalent to MOV %g0, %g0 NOPNOP do nothing Logical Not NotNot %rA Not %o4 Or %rA,%rB Bitwise Logical orPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0 Prefix PFXPFX 3 affects next instruction Read Control Register RdctlRdctl %rA Restore Caller’s Register Window Restore RET Restore restores caller’s register windowEquivalent to JMP %i7 Rotate Left Through Carry RLC Rotate Right Through Carry RRC Save Caller’s Register Window SaveSave %sp,-IMM8 Sign Extend 16-bit Value SEXT16SEXT16 %rA Sign Extend 8-bit Value SEXT8SEXT8 %rA Skip If Register Bit Is SKP0 SKP1 %rA,IMM5 SKP1 Skip If Register Not Equal To SKPRnz Skip If Register Equals SKPRzSKPRz %rA SKPRz %o3 Skip On Condition Code SkpsSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d Store 16-Bit Data To Memory Static Half-Word-Offset Address ST16sST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1 Store 8-Bit Data To Memory Computed Byte-Pointer Address ST8dST8d %rA,%r0 FILL8 %r0,%g3 Store 8-bit Data To Memory Static Byte-Offset Address ST8sMovi %g4,12 Mem%g4 + 36 + STP Store 32-bit Data To Memory Pointer Addressing Mode STS Store 32-bit Data To Memory Stack Addressing ModeSTS %sp,IMM8,%rA STS16s Store 16-bit Data To Memory Stack-Addressing ModeSTS16s %sp,IMM9,%r0 STS8s Store 8-bit Data To Memory Stack-Addressing ModeSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0 Subtract SUBSUB %rA,%rB Subtract Immediate SubiSubi %rB,IMM5 Swap Unconditional Trap Trap Trap Return Tret Write Control Register Wrctl Bitwise Logical Exclusive or XORXOR %rA,%rB 106 Numerics Index Index Index 110