Nios Embedded Processor
Nios Embedded Processor Programmer’s Reference Manual
Revision Date Description
Revision History
Information Type Access USA & Canada All Other Locations
How to Contact Altera
Conventions
Typographic Conventions
Visual Cue Meaning
Courier type
Altera Corporation
Contents
Viii
Bit Instruction Set
Index 107
Contents
Altera Corporation
List of Tables
Xii
Audience
Nios CPU Architecture
Nios CPU Details Bit Nios CPU
Register Groups
General-Purpose Registers
Clrie
Programmer’s Model
K Register
Program Counter
Control Registers
Interrrupt Enable IE
Condition Code Flags
Condition Code Flags
Memory Access Overview
Address Contents
Typical 32-bit Nios CPU Program/Data Memory at Address
Code Example 1 Reading a Single Byte from Memory
Writing to Memory or Peripherals
Bit Immediate Value
Addressing Modes
Code Example 3 The Addi Instruction Used with/without a PFX
Instructions Using 5/16-bit Immediate Values
Full Width Register-Indirect
Instructions Using Full Width Register-indirect Addressing
Partial Width Register-Indirect
Instruction Address Register Data Register
Partial Width Register-Indirect with Offset
Full Width Register-Indirect with Offset
Instruction Address Register
Offset Range without PFX
Relative-Branch Instructions
Instruction Address
Byte/Half-word Index Range
Absolute-Jump Instructions
Trap Instructions
Conditional Instructions
Exception Vector Table
Exception Handling Overview
Internal Exception Sources
External Hardware Interrupt Sources
Register Window Overflow
Exception Processing Sequence
Direct Software Exceptions Trap Instructions
Register Window Usage
Simple and Complex Exception Handlers
Return-Address
Pipeline Implementation
Branch Delay Slots
BR Branch Delay Slot Example
Pipeline Operation
Direct CWP Manipulation
Notation Meaning
Notation Details
Instruction Format Sheet 1
Instruction Format Sheet 2
Opcode Mnemonic Format Summary
Bit Major Opcode Table Sheet 1
USR0
Bit Major Opcode Table Sheet 2
MUL
Bit Major Opcode Table Sheet 3
GNU Compiler/Assembler Pseudo-instructions
Psuedo-Instruction
Operator Description Operation
Altera Corporation
Bit Instruction Set
Absolute Value
ABS
ABS %rA
ABS %r6
Add Without Carry
ADD
ADD %rA,%rB
ADD %L3,%g0 ADD %g0 to %L3
Add Immediate
Addi
%rA,%rB
Bitwise Logical
PFX %hiconst
PFX %hi16383
Bitwise Logical and not
Andn
PFX %hiconst Andn %rA,%loconst
PFX %hi16384
Arithmetic Shift Right
ASR
Arithmetic Shift Right Immediate
Asri
Bgen %rA,IMM5
Bit Generate
BR MainLoop
Branch
BSR
Branch To Subroutine
BSR SendCharacter
Call Subroutine
Call
CMP %rA,%rB
Compare
Compare Immediate
Cmpi
Cmpi & %rA,IMM5
Cmpi %i3,24 compare %i3 to
Half-Word Extract Dynamic
EXT16d
EXT16d %rA,%rB
LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC
Half-Word Extract Static
EXT16s
EXT16s %rA,IMM1
EXT16s %L3,1 %L3 gets upper short int of itself
Byte-Extract Dynamic
EXT8d
EXT8d %rA,%rB
LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC
Byte-Extract Static
EXT8s
EXT8s %rA,IMM2
EXT8s %g6,3 %g6 gets the 3rd byte of itself
Half-Word Fill
FILL16
FILL16 %r0,%rA
FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15
Byte-Fill
FILL8
FILL8 %r0,%rA
FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7
IF0
Equivalent to SKP1 Instruction
IF0 %rA,IMM5
Equivalent to SKP0 Instruction
IF1
IFRnz
Equivalent to SKPRz Instruction
IFRnz %rA IFRnz %o3
Equivalent to SKPRnz Instruction
IFRz
Conditionally Execute Next Instruction
IFS
Computed Jump
JMP
JMP %rA
JMP %o7 return
Word offset
Load 32-bit Data From Memory
Load 32-bit Data From Memory Pointer Addressing Mode
LDP
LDP %o3,%L2,3 Load %o3 from %L2 +
LDS
Lret
Equivalent to JMP %o7
Lret return
Logical Shift Left
LSL
LSL %rA,%rB
LSL %L3,%g0 Shift %L3 left by %g0 bits
Logical Shift Left Immediate
Lsli
Logical Shift Right
LSR
Logical Shift Right Immediate
Lsri
Register-to-Register Move
MOV
MOV %rA,%rB
MOV %o0,%L3 copy %L3 into %o0
Movhi
Move Immediate Into High Half-Word
Movhi %rA,IMM5
Movi
Move Immediate
Movi %rA,IMM5
Multiply-Step
Mstep
Mstep %rA
Mstep %r1
Multiply
MUL %rA
MUL %i5
Arithmetic Negation
NEG
NEG %rA
NEG %o4
NOP
Equivalent to MOV %g0, %g0
NOP do nothing
Logical Not
Not
Not %rA
Not %o4
Or %rA,%rB
Bitwise Logical or
PFX %hiconst Or %ra,%loconst
Or %i0,%i1 or %i1 into %i0
PFX
Prefix
PFX 3 affects next instruction
Rdctl
Read Control Register
Rdctl %rA
Restore Caller’s Register Window
Restore
Restore restores caller’s register window
RET
Equivalent to JMP %i7
Rotate Left Through Carry
RLC
Rotate Right Through Carry
RRC
Save
Save Caller’s Register Window
Save %sp,-IMM8
SEXT16
Sign Extend 16-bit Value
SEXT16 %rA
SEXT8
Sign Extend 8-bit Value
SEXT8 %rA
Skip If Register Bit Is
SKP0
SKP1 %rA,IMM5
SKP1
Skip If Register Not Equal To
SKPRnz
SKPRz
Skip If Register Equals
SKPRz %rA SKPRz %o3
Skps
Skip On Condition Code
Skps ccIMM4 Skps ccne
Store 32-bit Data To Memory
ST16d
Store 16-Bit Data To Memory Static Half-Word-Offset Address
ST16s
ST16s %rA,%r0,IMM1
PFX Y ST16s %rA,%r0,Y 1
Store 8-Bit Data To Memory Computed Byte-Pointer Address
ST8d
ST8d %rA,%r0
FILL8 %r0,%g3
Store 8-bit Data To Memory Static Byte-Offset Address
ST8s
Movi %g4,12
Mem%g4 + 36 +
STP
Store 32-bit Data To Memory Pointer Addressing Mode
Store 32-bit Data To Memory Stack Addressing Mode
STS
STS %sp,IMM8,%rA
Store 16-bit Data To Memory Stack-Addressing Mode
STS16s
STS16s %sp,IMM9,%r0
STS8s
Store 8-bit Data To Memory Stack-Addressing Mode
STS8s %sp,IMM10,%r0
FILL8 %r0,%rX STS8s %sp,Y,%r0
SUB
Subtract
SUB %rA,%rB
Subi
Subtract Immediate
Subi %rB,IMM5
Swap
Unconditional Trap
Trap
Trap Return
Tret
Write Control Register
Wrctl
XOR
Bitwise Logical Exclusive or
XOR %rA,%rB
106
Numerics
Index
Index
Index
110