Excalibur electronic A-MNL-NIOSPROG-01.1 manual Relative-Branch Instructions, Instruction Address

Overview

These instructions may each only use the stack pointer, register %sp (equivalent to %o6), as their address register, and may only use register %r0 (equivalent to %g0, but must be called %r0 in the assembly instruction) as the data register. These instructions are convenient to use with the FILL8 or FILL16 (32-bit Nios CPU only) instructions.

Table 14. Instructions Using Partial Width Register-indirect with Offset Addressing

Instruction	Address	Data Register	Byte/Half-word	Index Range
	Register		Selection
STS8s	%sp	%r0	Immediate	0..1023 bytes
STS16s*	%sp	%r0	Immediate	0..511 half-words

Program-Flow Control

*32-bit Nios CPU only

The topics in this section includes a description of the following:

■Two relative-branch instructions (BR and BSR)

■Two absolute-jump instructions (JMP and CALL)

■Two trap instructions (TRET and TRAP)

■Five conditional instructions (SKP, SKP0, SKP1, SKPRz and SKPRnz)

Relative-Branch Instructions

There are two relative-branch instructions: BR and BSR. The branch target address is computed from the current program-counter (i.e. the address of the BR instruction itself) and the IMM11 instruction field. Details of the branch-offset computation are provided in the description of the BR and BSR instructions. See “BR” on page 42 and “BSR” on page 43. BSR is identical to BR except that the return-address is saved in %o7. Details of the return-address computation are provided in the description of the BSR instruction. Both BR and BSR are unconditional. Conditional branches are implemented by preceding BR or BSR with a SKP-type instruction.

Both BR and BSR instructions have branch delay slot behavior: The instruction immediately following a BR or BSR is executed after BR or BSR, but before the instruction at the branch-target. See “Branch Delay Slots” on page 23 for more information. The branch range of the BR and BSR instructions is forward by 2048 bytes, or backwards by 2046 bytes relative to the address of the BR or BSR instruction.

14 Altera Corporation