Excalibur electronic A-MNL-NIOSPROG-01.1 manual Audience, Nios CPU Architecture

Models: A-MNL-NIOSPROG-01.1

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Introduction

Nios CPU Overview

Overview

The NiosTM embedded processor is a soft core CPU optimized for programmable logic and system-on-a-programmable chip (SOPC) integration. It is a configurable, general-purpose RISC processor that can be combined with user logic and programmed into an Altera programmable logic device (PLD). The Nios CPU can be configured for a wide range of applications. A 16-bit Nios CPU core running a small program out of an on-chip ROM makes an effective sequencer or controller, taking the place of a hard-coded state machine. A 32-bit Nios CPU core with external FLASH program storage and large external main memory is a powerful 32-bit embedded processor system.

Audience

This reference manual is for software and hardware engineers creating system design modules using the Excalibur Development Kit, featuring the Nios embedded processor. This manual assumes you are familiar with electronics, microprocessors, and assembly language programming. To become familiar with the conventions used with the Nios CPU, see Table 16 on page 25.

The Nios CPU is a pipelined, single-issue RISC processor in which most instructions run in a single clock cycle. The Nios instruction set is targeted for compiled embedded applications. The 16-bit and 32-bit Nios CPU have native-word sizes of 16 bits and 32 bits, respectively, meaning the 16-bit Nios CPU has a native-word size of a half-word, while the 32-bit Nios CPU has a native-word size of a word. In Nios, byte refers to an 8-bit quantity, half-word refers to a 16-bit quantity, and word refers to a 32-bit quantity. The Nios family of soft core processors includes 32-bit and 16-bit architecture variants.

Table 4. Nios CPU Architecture

Nios CPU Details

32-bit Nios CPU

16-bit Nios CPU

 

 

 

Data bus size (bits)

32

16

 

 

 

ALU width (bits)

32

16

 

 

 

Internal register width (bits)

32

16

 

 

 

Address bus size (bits)

33

17

 

 

 

Instruction size (bits)

16

16

 

 

 

Logic cells (typical)

1700

1100

 

 

 

fmax (EP20K200E –1)

Up to 50MHz

Up to 50MHz

1

Overview

Altera Corporation

1

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Audience, Nios CPU Architecture, Nios CPU Details Bit Nios CPU