Excalibur electronic A-MNL-NIOSPROG-01.1 manual ST16d

32-Bit Instruction Set

ST16d

Store 16-Bit Data To Memory (Computed Half-Word Pointer Address)

Operation:

Not preceded by PFX :

hnMem32[align32(RA)] ← hnR0 where n = RA[1]

Preceded by PFX:

hnMem32[align32(RA + (σ(K) × 4))] ← hnR0 where n = RA[1]

Assembler Syntax:

ST16d [%rA],%r0

Example:

Not preceded by PFX:

FILL16 %r0,%g7 ; duplicate short of %g7 across %r0

ST16d [%o3],%r0 ; store %o3[1]th short int from

; %r0 to [%o3]

; second operand can only be %r0

Preceded by PFX:

FILL16 %r0,%g3

PFX 5

ST16d [%o3],%r0 ; same as above, offset

; 20 bytes in memory

Description:

Not preceded by PFX:

Stores one of the two half-words of %r0 to memory at the half-word-aligned

address given by RA. The bits RA[1] selects which half-word in %r0 get stored

(half-word 1 is the most-significant). RA[0] is ignored.

ST16d may be used in combination with FILL16 to implement a two-instruction

half-word-store operation. Given a half-word held in bits 15..0 of any register %rX,

the following sequence writes this half-word to memory at the half-word-aligned

address given by RA:

FILL16 %r0,%rX

ST16d [%rA],%r0

Preceded by PFX:

The value in K is sign-extended and used as a word-scaled, signed offset. This

offset is added to the base-address RA and data is written to the resulting byte-

address.

Condition Codes:

Flags: Unaffected

N

V

Z

C

−

−

−

−

Instruction Format:

Rw

Instruction Fields:

A = Register index of operand RA

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

1

1

1

1

1

1

0

0

0

1

A

2

32-Bit Instruction Set

Altera Corporation 91