Bitwise Logical or | Excalibur electronic A-MNL-NIOSPROG-01.1

32-Bit Instruction Set

OR

Bitwise Logical OR

Operation:							Not preceded by PFX:
							RA ← RA RB
							Preceded by PFX:
							RA ← RA (0x00.00 : K : IMM5)
Assembler Syntax:							Not preceded by PFX:
							OR %rA,%rB
							Preceded by PFX:
							PFX %hi(const)
							OR %ra,%lo(const)
Example:							Not preceded by PFX:
							OR %i0,%i1 ; OR %i1 into %i0
							Preceded by PFX:
							PFX %hi(3333)
							OR %i0,%lo(3333) ; OR %i0 with 3333
Description:							Not preceded by PFX:
							Logically-OR the individual bits in RA with the corresponding bits in RB; store the
							result in RA.
							Preceded by PFX:
							When prefixed, the RB operand is replaced by an immediate constant formed by
							concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This
							16-bit value is zero-extended to 32 bits, then bitwise-ORed with RA. The result is
							written back into RA.
Condition Codes:							Flags:
							N		V		Z		C

							∆		–		∆		–

							N: Result bit 31
							Z: Set if result is zero; cleared otherwise
Instruction Format:							RR, Ri5
Instruction Fields							A = Register index of operand RA
							B = Register index of operand RB
							IMM5 = 5-bit immediate value
Not preceded by PFX (RR)
15	14	13		12		11		10			9		8		7	6	5		4	3	2	1	0

0	1	0		0		0		0							B						A

Preceded by PFX (Ri5)
15	14	13		12		11		10			9		8		7	6	5		4	3	2	1	0

0	1	0		0		0		0							IMM5						A

2

32-Bit Instruction Set

Altera Corporation

75

Image 87

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Bitwise Logical or, Or %rA,%rB, PFX %hiconst Or %ra,%loconst, PFX %hi3333

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision History Information Type Access USA & Canada All Other Locations How to Contact Altera Courier type Typographic ConventionsConventions Visual Cue Meaning Altera Corporation Contents Viii Bit Instruction Set Index 107 Contents Altera Corporation List of Tables Xii Audience Nios CPU ArchitectureNios CPU Details Bit Nios CPU Register Groups General-Purpose Registers Clrie Programmer’s Model K Register Program CounterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code Flags Memory Access Overview Address ContentsTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing Modes Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate Values Instruction Address Register Data Register Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Partial Width Register-Indirect Offset Range without PFX Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Instruction Address Register Relative-Branch Instructions Instruction AddressByte/Half-word Index Range Absolute-Jump Instructions Trap InstructionsConditional Instructions Exception Vector Table Exception Handling Overview Internal Exception Sources External Hardware Interrupt Sources Register Window Overflow Exception Processing Sequence Direct Software Exceptions Trap Instructions Register Window Usage Simple and Complex Exception Handlers Return-Address Pipeline Implementation Branch Delay Slots BR Branch Delay Slot ExamplePipeline Operation Direct CWP Manipulation Notation Meaning Notation Details Instruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1 USR0 Bit Major Opcode Table Sheet 2 MUL Bit Major Opcode Table Sheet 3 GNU Compiler/Assembler Pseudo-instructions Psuedo-InstructionOperator Description Operation Altera Corporation Bit Instruction Set ABS %r6 ABSAbsolute Value ABS %rA ADD %L3,%g0 ADD %g0 to %L3 ADDAdd Without Carry ADD %rA,%rB Add Immediate Addi PFX %hi16383 Bitwise Logical%rA,%rB PFX %hiconst PFX %hi16384 AndnBitwise Logical and not PFX %hiconst Andn %rA,%loconst Arithmetic Shift Right ASR Arithmetic Shift Right Immediate Asri Bgen %rA,IMM5 Bit Generate BR MainLoop Branch BSR Branch To SubroutineBSR SendCharacter Call Subroutine Call CMP %rA,%rB Compare Cmpi %i3,24 compare %i3 to CmpiCompare Immediate Cmpi & %rA,IMM5 LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16dHalf-Word Extract Dynamic EXT16d %rA,%rB EXT16s %L3,1 %L3 gets upper short int of itself EXT16sHalf-Word Extract Static EXT16s %rA,IMM1 LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8dByte-Extract Dynamic EXT8d %rA,%rB EXT8s %g6,3 %g6 gets the 3rd byte of itself EXT8sByte-Extract Static EXT8s %rA,IMM2 FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL16Half-Word Fill FILL16 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 FILL8Byte-Fill FILL8 %r0,%rA IF0 Equivalent to SKP1 InstructionIF0 %rA,IMM5 Equivalent to SKP0 Instruction IF1 IFRnz Equivalent to SKPRz InstructionIFRnz %rA IFRnz %o3 Equivalent to SKPRnz Instruction IFRz Conditionally Execute Next Instruction IFS JMP %o7 return JMPComputed Jump JMP %rA Word offset Load 32-bit Data From Memory Load 32-bit Data From Memory Pointer Addressing Mode LDPLDP %o3,%L2,3 Load %o3 from %L2 + LDS Lret Equivalent to JMP %o7Lret return LSL %L3,%g0 Shift %L3 left by %g0 bits LSLLogical Shift Left LSL %rA,%rB Logical Shift Left Immediate Lsli Logical Shift Right LSR Logical Shift Right Immediate Lsri MOV %o0,%L3 copy %L3 into %o0 MOVRegister-to-Register Move MOV %rA,%rB Movhi Move Immediate Into High Half-WordMovhi %rA,IMM5 Movi Move ImmediateMovi %rA,IMM5 Mstep %r1 MstepMultiply-Step Mstep %rA Multiply MUL %rAMUL %i5 NEG %o4 NEGArithmetic Negation NEG %rA NOP Equivalent to MOV %g0, %g0NOP do nothing Not %o4 NotLogical Not Not %rA Or %i0,%i1 or %i1 into %i0 Bitwise Logical orOr %rA,%rB PFX %hiconst Or %ra,%loconst PFX PrefixPFX 3 affects next instruction Rdctl Read Control RegisterRdctl %rA Restore Caller’s Register Window Restore Restore restores caller’s register window RETEquivalent to JMP %i7 Rotate Left Through Carry RLC Rotate Right Through Carry RRC Save Save Caller’s Register WindowSave %sp,-IMM8 SEXT16 Sign Extend 16-bit ValueSEXT16 %rA SEXT8 Sign Extend 8-bit ValueSEXT8 %rA Skip If Register Bit Is SKP0 SKP1 %rA,IMM5 SKP1 Skip If Register Not Equal To SKPRnz SKPRz Skip If Register EqualsSKPRz %rA SKPRz %o3 Skps Skip On Condition CodeSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d PFX Y ST16s %rA,%r0,Y 1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address ST16s %rA,%r0,IMM1 FILL8 %r0,%g3 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address ST8d %rA,%r0 Mem%g4 + 36 + ST8sStore 8-bit Data To Memory Static Byte-Offset Address Movi %g4,12 STP Store 32-bit Data To Memory Pointer Addressing Mode Store 32-bit Data To Memory Stack Addressing Mode STSSTS %sp,IMM8,%rA Store 16-bit Data To Memory Stack-Addressing Mode STS16sSTS16s %sp,IMM9,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s STS8s %sp,IMM10,%r0 SUB SubtractSUB %rA,%rB Subi Subtract ImmediateSubi %rB,IMM5 Swap Unconditional Trap Trap Trap Return Tret Write Control Register Wrctl XOR Bitwise Logical Exclusive orXOR %rA,%rB 106 Numerics Index Index Index 110