Overview

Pipeline Implementation

Complex Exception Handlers

An exception handler is considered complex if it violates any of the requirements of a simple exception handler, listed above. Complex exception handlers allow nested exception handling and the execution of more complex code (e.g. subroutines that SAVE and RESTORE). A complex exception handler has the following additional responsibilities:

It must preserve the contents of ISTATUS before re-enabling interrupts. For example, ISTATUS could be saved on the stack.

It must check CWP before re-enabling interrupts to be sure CWP is at or above LO_LIMIT. If CWP is below LO_LIMIT, it must take an action to open up more available register windows (e.g., save the register file contents to RAM), or it must signal an error.

It must re-enable interrupts subject to the above two conditions before executing any SAVE or RESTORE instructions or calling any subroutines that execute any SAVE or RESTORE instructions.

Prior to returning control to the interruptee, it must restore the contents of the ISTATUS register, including any adjustments to CWP if the register-window has been deliberately shifted.

Prior to returning control to the interruptee, it must restore the contents of the interruptee’s register window.

This topics in this section include a description of the following:

Nios CPU pipeline

Exposed pipeline branch delay and direct CWP manipulation

Figure 4. Nios CPU Block Diagram

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Pipeline Implementation