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| Overview |
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Table 16. Notation Details |
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Notation | Meaning | Notation | Meaning |
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X ← Y | X is written with Y | X >> n | The value X after being |
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| positions |
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∅ ← e | Expression e is evaluated, and the result | X << n | The value X after being |
| is discarded |
| positions |
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RA | One of the 32 visible registers, selected | bnX | The nth byte |
| by the |
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| b1X = X[15..8], b2X = X[23..16], and |
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| b3X = X[31..24] |
RB | One of the 32 visible registers, selected | hnX | The nth |
| by the |
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| h1X = X[31..16] |
RP | One of the 4 | X & Y | Bitwise logical AND |
| registers, selected by the |
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| the instruction word |
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IMMn | An | X Y | Bitwise logical OR |
| the instruction word |
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K | The | X ⊕ Y | Bitwise logical exclusive OR |
| can only be set by a PFX instruction) |
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0xnn.mm | Hexadecimal notation (decimal points not | ~X | Bitwise logical NOT (one’s complement) |
| significant, added for clarity) |
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X : Y | X | The absolute value of X | |
| e.g.: (0x12 : 0x34) = 0x1234 |
| (i.e. |
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{e1, e2} | Conditional expression. Evaluates to e2 | Mem32[X] | The aligned |
| if previous instruction was PFX, |
| external memory, starting at byte address |
| e1 otherwise |
| X |
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σ(X) | X after being | Mem16[X] | The aligned |
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| address X |
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X[n] | The nth bit of X (n = 0 means LSB) | align16(X) | X & 0xFF.FE, which is the integer value X |
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| forced into |
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| truncation |
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X[n..m] | Consecutive bits n through m of X | align32(X) | X & 0xFF.FF.FF.FC, which is the integer |
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| value X forced into |
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| truncation |
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C | The C (carry) flag in the STATUS register |
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CTLk | One of the 2047 control registers selected |
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| by K |
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1
Overview
Altera Corporation | 25 |