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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Half-Word Extract Dynamic, EXT16d %rA,%rB

Models: A-MNL-NIOSPROG-01.1

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	32-Bit Instruction Set

	EXT16d
	Half-Word Extract (Dynamic)
Operation:	RA ← (0x00.00 : hnRA) where n = RB[1]
Assembler Syntax:	EXT16d %rA,%rB
Example:	LD %i3,[%i4] ; get 32 bits from [%i4 & 0xFF.FF.FF.FC]
	EXT16d %i3,%i4 ; extract short int at %i4
Description:	Extracts one of the two half-words in RA. The half-word to-be-extracted is chosen
	by bit 1 of RB. The selected half-word is written into bits 15..0 of RA, and the
	more-significant bits 31..16 are set to zero.

2

32-Bit Instruction Set

Condition Codes:						Flags: Unaffected
						N		V		Z		C

						−		−		−		−
Instruction Format:
Instruction Format:						RR
Instruction Fields:						A = Register index of operand RA
						B = Register index of operand RB
15	14	13		12	11		10			9		8		7	6	5	4	3	2	1	0

0	1	1		0	1		0							B					A

Altera Corporation

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Half-Word Extract Dynamic, EXT16d %rA,%rB

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision HistoryInformation Type Access USA & Canada All Other Locations How to Contact AlteraCourier type Typographic ConventionsConventions Visual Cue MeaningAltera Corporation Contents Viii Bit Instruction SetIndex 107 ContentsAltera Corporation List of Tables Xii Nios CPU Details Bit Nios CPU AudienceNios CPU Architecture Register Groups General-Purpose RegistersClrie Programmer’s ModelControl Registers K RegisterProgram Counter Interrrupt Enable IE Condition Code Flags Condition Code FlagsTypical 32-bit Nios CPU Program/Data Memory at Address Memory Access OverviewAddress Contents Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing ModesCode Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate ValuesInstruction Address Register Data Register Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Partial Width Register-IndirectOffset Range without PFX Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Instruction Address RegisterByte/Half-word Index Range Relative-Branch InstructionsInstruction Address Conditional Instructions Absolute-Jump InstructionsTrap Instructions Exception Vector Table Exception Handling OverviewInternal Exception Sources External Hardware Interrupt SourcesRegister Window Overflow Exception Processing Sequence Direct Software Exceptions Trap InstructionsRegister Window Usage Simple and Complex Exception Handlers Return-AddressPipeline Implementation Pipeline Operation Branch Delay SlotsBR Branch Delay Slot Example Direct CWP Manipulation Notation Meaning Notation DetailsInstruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1USR0 Bit Major Opcode Table Sheet 2MUL Bit Major Opcode Table Sheet 3Operator Description Operation GNU Compiler/Assembler Pseudo-instructionsPsuedo-Instruction Altera Corporation Bit Instruction Set ABS %r6 ABSAbsolute Value ABS %rAADD %L3,%g0 ADD %g0 to %L3 ADDAdd Without Carry ADD %rA,%rBAdd Immediate AddiPFX %hi16383 Bitwise Logical%rA,%rB PFX %hiconstPFX %hi16384 AndnBitwise Logical and not PFX %hiconst Andn %rA,%loconstArithmetic Shift Right ASRArithmetic Shift Right Immediate AsriBgen %rA,IMM5 Bit GenerateBR MainLoop BranchBSR SendCharacter BSRBranch To Subroutine Call Subroutine CallCMP %rA,%rB CompareCmpi %i3,24 compare %i3 to CmpiCompare Immediate Cmpi & %rA,IMM5LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16dHalf-Word Extract Dynamic EXT16d %rA,%rBEXT16s %L3,1 %L3 gets upper short int of itself EXT16sHalf-Word Extract Static EXT16s %rA,IMM1LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8dByte-Extract Dynamic EXT8d %rA,%rBEXT8s %g6,3 %g6 gets the 3rd byte of itself EXT8sByte-Extract Static EXT8s %rA,IMM2FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL16Half-Word Fill FILL16 %r0,%rAFILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 FILL8Byte-Fill FILL8 %r0,%rAIF0 %rA,IMM5 IF0Equivalent to SKP1 Instruction Equivalent to SKP0 Instruction IF1IFRnz %rA IFRnz %o3 IFRnzEquivalent to SKPRz Instruction Equivalent to SKPRnz Instruction IFRzConditionally Execute Next Instruction IFSJMP %o7 return JMPComputed Jump JMP %rAWord offset Load 32-bit Data From MemoryLDP %o3,%L2,3 Load %o3 from %L2 + Load 32-bit Data From Memory Pointer Addressing ModeLDP LDS Lret return LretEquivalent to JMP %o7 LSL %L3,%g0 Shift %L3 left by %g0 bits LSLLogical Shift Left LSL %rA,%rBLogical Shift Left Immediate LsliLogical Shift Right LSRLogical Shift Right Immediate LsriMOV %o0,%L3 copy %L3 into %o0 MOVRegister-to-Register Move MOV %rA,%rBMovhi %rA,IMM5 MovhiMove Immediate Into High Half-Word Movi %rA,IMM5 MoviMove Immediate Mstep %r1 MstepMultiply-Step Mstep %rAMUL %i5 MultiplyMUL %rA NEG %o4 NEGArithmetic Negation NEG %rANOP do nothing NOPEquivalent to MOV %g0, %g0 Not %o4 NotLogical Not Not %rAOr %i0,%i1 or %i1 into %i0 Bitwise Logical orOr %rA,%rB PFX %hiconst Or %ra,%loconstPFX 3 affects next instruction PFXPrefix Rdctl %rA RdctlRead Control Register Restore Caller’s Register Window RestoreEquivalent to JMP %i7 Restore restores caller’s register windowRET Rotate Left Through Carry RLCRotate Right Through Carry RRCSave %sp,-IMM8 SaveSave Caller’s Register Window SEXT16 %rA SEXT16Sign Extend 16-bit Value SEXT8 %rA SEXT8Sign Extend 8-bit Value Skip If Register Bit Is SKP0SKP1 %rA,IMM5 SKP1Skip If Register Not Equal To SKPRnzSKPRz %rA SKPRz %o3 SKPRzSkip If Register Equals Skps ccIMM4 Skps ccne SkpsSkip On Condition Code Store 32-bit Data To Memory ST16d PFX Y ST16s %rA,%r0,Y 1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address ST16s %rA,%r0,IMM1FILL8 %r0,%g3 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address ST8d %rA,%r0Mem%g4 + 36 + ST8sStore 8-bit Data To Memory Static Byte-Offset Address Movi %g4,12STP Store 32-bit Data To Memory Pointer Addressing ModeSTS %sp,IMM8,%rA Store 32-bit Data To Memory Stack Addressing ModeSTS STS16s %sp,IMM9,%r0 Store 16-bit Data To Memory Stack-Addressing ModeSTS16s FILL8 %r0,%rX STS8s %sp,Y,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s STS8s %sp,IMM10,%r0SUB %rA,%rB SUBSubtract Subi %rB,IMM5 SubiSubtract Immediate Swap Unconditional Trap TrapTrap Return TretWrite Control Register WrctlXOR %rA,%rB XORBitwise Logical Exclusive or 106 Numerics IndexIndex Index 110