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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Branch, BR MainLoop

Models: A-MNL-NIOSPROG-01.1

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32-Bit Instruction Set

Branch

Operation:					PC ← PC + ((σ(IMM11) + 1) << 1)
Assembler Syntax:					BR addr
Example:					BR MainLoop
					NOP ; (delay slot)
Description:					The offset given by IMM11 is interpreted as a signed number of half-words
					(instructions) relative to the instruction immediately following BR. Program control
					is transferred to instruction at this offset.
Condition Codes:					Flags: Unaffected
					N		V	Z	C

					−		−	−	−
Delay Slot Behavior:
Delay Slot Behavior:					The instruction immediately following BR (BR’s delay slot) is executed after BR,
					but before the destination instruction. There are restrictions on which instructions
					may be used as a delay slot. (Refer to “Branch Delay Slots” on page 23)
Instruction Format:					i11
Instruction Fields:					IMM11 = 11-bit immediate value
15	14	13	12	11		10		9	8	7	6	5	4	3	2	1	0

1	0	0	0	0								IMM11

42	Altera Corporation

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Branch, BR MainLoop

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date DescriptionHow to Contact Altera Information Type Access USA & Canada All Other LocationsVisual Cue Meaning Typographic ConventionsConventions Courier typeAltera Corporation Contents Bit Instruction Set ViiiContents Index 107Altera Corporation List of Tables Xii Audience Nios CPU ArchitectureNios CPU Details Bit Nios CPU General-Purpose Registers Register GroupsProgrammer’s Model ClrieK Register Program CounterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code FlagsMemory Access Overview Address ContentsTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate ValueInstructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFXPartial Width Register-Indirect Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Instruction Address Register Data RegisterInstruction Address Register Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Offset Range without PFXRelative-Branch Instructions Instruction AddressByte/Half-word Index Range Absolute-Jump Instructions Trap InstructionsConditional Instructions Exception Handling Overview Exception Vector TableExternal Hardware Interrupt Sources Internal Exception SourcesRegister Window Overflow Direct Software Exceptions Trap Instructions Exception Processing SequenceRegister Window Usage Return-Address Simple and Complex Exception HandlersPipeline Implementation Branch Delay Slots BR Branch Delay Slot ExamplePipeline Operation Direct CWP Manipulation Notation Details Notation MeaningInstruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format SummaryBit Major Opcode Table Sheet 2 USR0Bit Major Opcode Table Sheet 3 MULGNU Compiler/Assembler Pseudo-instructions Psuedo-InstructionOperator Description Operation Altera Corporation Bit Instruction Set ABS %rA ABSAbsolute Value ABS %r6ADD %rA,%rB ADDAdd Without Carry ADD %L3,%g0 ADD %g0 to %L3Addi Add ImmediatePFX %hiconst Bitwise Logical%rA,%rB PFX %hi16383PFX %hiconst Andn %rA,%loconst AndnBitwise Logical and not PFX %hi16384ASR Arithmetic Shift RightAsri Arithmetic Shift Right ImmediateBit Generate Bgen %rA,IMM5Branch BR MainLoopBSR Branch To SubroutineBSR SendCharacter Call Call SubroutineCompare CMP %rA,%rBCmpi & %rA,IMM5 CmpiCompare Immediate Cmpi %i3,24 compare %i3 toEXT16d %rA,%rB EXT16dHalf-Word Extract Dynamic LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FCEXT16s %rA,IMM1 EXT16sHalf-Word Extract Static EXT16s %L3,1 %L3 gets upper short int of itselfEXT8d %rA,%rB EXT8dByte-Extract Dynamic LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FCEXT8s %rA,IMM2 EXT8sByte-Extract Static EXT8s %g6,3 %g6 gets the 3rd byte of itselfFILL16 %r0,%rA FILL16Half-Word Fill FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15FILL8 %r0,%rA FILL8Byte-Fill FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7IF0 Equivalent to SKP1 InstructionIF0 %rA,IMM5 IF1 Equivalent to SKP0 InstructionIFRnz Equivalent to SKPRz InstructionIFRnz %rA IFRnz %o3 IFRz Equivalent to SKPRnz InstructionIFS Conditionally Execute Next InstructionJMP %rA JMPComputed Jump JMP %o7 returnLoad 32-bit Data From Memory Word offsetLoad 32-bit Data From Memory Pointer Addressing Mode LDPLDP %o3,%L2,3 Load %o3 from %L2 + LDS Lret Equivalent to JMP %o7Lret return LSL %rA,%rB LSLLogical Shift Left LSL %L3,%g0 Shift %L3 left by %g0 bitsLsli Logical Shift Left ImmediateLSR Logical Shift RightLsri Logical Shift Right ImmediateMOV %rA,%rB MOVRegister-to-Register Move MOV %o0,%L3 copy %L3 into %o0Movhi Move Immediate Into High Half-WordMovhi %rA,IMM5 Movi Move ImmediateMovi %rA,IMM5 Mstep %rA MstepMultiply-Step Mstep %r1Multiply MUL %rAMUL %i5 NEG %rA NEGArithmetic Negation NEG %o4NOP Equivalent to MOV %g0, %g0NOP do nothing Not %rA NotLogical Not Not %o4PFX %hiconst Or %ra,%loconst Bitwise Logical orOr %rA,%rB Or %i0,%i1 or %i1 into %i0PFX PrefixPFX 3 affects next instruction Rdctl Read Control RegisterRdctl %rA Restore Restore Caller’s Register WindowRestore restores caller’s register window RETEquivalent to JMP %i7 RLC Rotate Left Through CarryRRC Rotate Right Through CarrySave Save Caller’s Register WindowSave %sp,-IMM8 SEXT16 Sign Extend 16-bit ValueSEXT16 %rA SEXT8 Sign Extend 8-bit ValueSEXT8 %rA SKP0 Skip If Register Bit IsSKP1 SKP1 %rA,IMM5SKPRnz Skip If Register Not Equal ToSKPRz Skip If Register EqualsSKPRz %rA SKPRz %o3 Skps Skip On Condition CodeSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d ST16s %rA,%r0,IMM1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address PFX Y ST16s %rA,%r0,Y 1ST8d %rA,%r0 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address FILL8 %r0,%g3Movi %g4,12 ST8sStore 8-bit Data To Memory Static Byte-Offset Address Mem%g4 + 36 +Store 32-bit Data To Memory Pointer Addressing Mode STPStore 32-bit Data To Memory Stack Addressing Mode STSSTS %sp,IMM8,%rA Store 16-bit Data To Memory Stack-Addressing Mode STS16sSTS16s %sp,IMM9,%r0 STS8s %sp,IMM10,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s FILL8 %r0,%rX STS8s %sp,Y,%r0SUB SubtractSUB %rA,%rB Subi Subtract ImmediateSubi %rB,IMM5 Swap Trap Unconditional TrapTret Trap ReturnWrctl Write Control RegisterXOR Bitwise Logical Exclusive orXOR %rA,%rB 106 Index NumericsIndex Index 110