Excalibur electronic A-MNL-NIOSPROG-01.1 manual Ldp, LDP %o3,%L2,3 Load %o3 from %L2 +

32-Bit Instruction Set

LDP

Load 32-bit Data From Memory (Pointer Addressing Mode)

Operation:

Not preceded by PFX:

RA ← Mem32[align32(RP + (IMM5 × 4))]

Preceded by PFX:

RA ← Mem32[align32(RP + (σ(K : IMM5) × 4))]

Assembler Syntax:

LDP %rA,[%rP,IMM5]

Example:

Not preceded by PFX:

LDP %o3,[%L2,3] ; Load %o3 from [%L2 + 12]

; second register operand must be

; one of %L0, %L1, %L2, or %L3

Preceded by PFX:

PFX %hi(100)

LDP %o3,[%L2,%lo(100)] ; load %o3 from [%L2 + 400]

Description:

Not preceded by PFX:

Loads a 32-bit data value from memory into RA. Data is always read from a word-

aligned address given by bits 31..2 of RP (the two LSBs of RP are ignored) plus

a 5-bit, unsigned, word-scaled offset given by IMM5.

This instruction is similar to LD, but additionally allows a positive 5-bit offset to be

applied to any of four base-pointers in a single instruction. The base-pointer must

be one of the four registers: %L0, %L1, %L2, or %L3.

Preceded by PFX:

A 16-bit offset is formed by concatenating the 11-bit K-register with IMM5 (5 bits).

The 16-bit offset (K : IMM5) is sign-extended to 32 bits, multiplied by four, and

added to bits 31..2 of RP to yield a word-aligned effective address.

Condition Codes:

Flags: Unaffected

N

V

Z

C

−

−

−

−

Instruction Format:

RPi5

Instruction Fields:

A = Register index of operand RA

IMM5 = 5-bit immediate value

P = Index of base-pointer register, less 16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

1

P

IMM5

A

60 Altera Corporation