ST8d %rA,%r0 | Excalibur electronic A-MNL-NIOSPROG-01.1 manual

32-Bit Instruction Set

ST8d

Store 8-Bit Data To Memory (Computed Byte-Pointer Address)

Operation:

Assembler Syntax: Example:

Not preceded by PFX:

bnMem32[align32(RA)] ← bnR0 where n = RA[1..0]

Preceded by PFX:

bnMem32[align32(RA + σ(K) × 4))] ← bnR0 where n = RA[1..0]

ST8d [%rA],%r0

Not preceded by PFX:

FILL8 %r0,%g7 ; duplicate low byte of %g7 across %r0 ST8d [%o3],%r0 ; store %o3[1..0]th byte from

;%r0 to [%o3]

;second operand can only be %r0

Preceded by PFX:

FILL8 %r0,%g3

PFX 5

ST8d [%o3],%r0 ; same as above, offset ; 20 bytes in memory

2

32-Bit Instruction Set

Description:						Not preceded by PFX:
						Stores one of the four bytes of %r0 to memory at the byte-address given by RA.
						The two bits RA[1..0] select which byte in %r0 get stored (byte 3 is the most-
						significant).
						ST8d may be used in combination with FILL8 to implement a two-instruction byte-
						store operation. Given a byte held in bits 7..0 of any register %rX, the following
						sequence writes this byte to memory at the byte-address given by RA:
								FILL8 %r0,%rX
								ST8d [%rA],%r0
						Preceded by PFX:
						The value in K is sign-extended and used as a word-scaled, signed offset. This
						offset is added to the base-address RA and data is written to the resulting byte-
						address.
Condition Codes:						Flags: Unaffected
						N		V		Z		C

						−		−		−		−
Instruction Format:						Rw
Instruction Fields:						A = Register index of operand RA
15	14	13		12	11		10			9		8			7		6	5	4	3	2	1	0

0	1	1		1	1		1			1			0		0		0	0			A

Altera Corporation

93

Image 105

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Store 8-Bit Data To Memory Computed Byte-Pointer Address, ST8d %rA,%r0

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision Date Description Revision History Information Type Access USA & Canada All Other Locations How to Contact Altera Conventions Typographic ConventionsVisual Cue Meaning Courier type Altera Corporation Contents Viii Bit Instruction Set Index 107 Contents Altera Corporation List of Tables Xii Audience Nios CPU ArchitectureNios CPU Details Bit Nios CPU Register Groups General-Purpose Registers Clrie Programmer’s Model K Register Program CounterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code Flags Memory Access Overview Address ContentsTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Bit Immediate Value Addressing Modes Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using 5/16-bit Immediate Values Full Width Register-Indirect Instructions Using Full Width Register-indirect AddressingPartial Width Register-Indirect Instruction Address Register Data Register Partial Width Register-Indirect with Offset Full Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFX Relative-Branch Instructions Instruction AddressByte/Half-word Index Range Absolute-Jump Instructions Trap InstructionsConditional Instructions Exception Vector Table Exception Handling Overview Internal Exception Sources External Hardware Interrupt Sources Register Window Overflow Exception Processing Sequence Direct Software Exceptions Trap Instructions Register Window Usage Simple and Complex Exception Handlers Return-Address Pipeline Implementation Branch Delay Slots BR Branch Delay Slot ExamplePipeline Operation Direct CWP Manipulation Notation Meaning Notation Details Instruction Format Sheet 1 Instruction Format Sheet 2 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 1 USR0 Bit Major Opcode Table Sheet 2 MUL Bit Major Opcode Table Sheet 3 GNU Compiler/Assembler Pseudo-instructions Psuedo-InstructionOperator Description Operation Altera Corporation Bit Instruction Set Absolute Value ABSABS %rA ABS %r6 Add Without Carry ADDADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3 Add Immediate Addi %rA,%rB Bitwise LogicalPFX %hiconst PFX %hi16383 Bitwise Logical and not AndnPFX %hiconst Andn %rA,%loconst PFX %hi16384 Arithmetic Shift Right ASR Arithmetic Shift Right Immediate Asri Bgen %rA,IMM5 Bit Generate BR MainLoop Branch BSR Branch To SubroutineBSR SendCharacter Call Subroutine Call CMP %rA,%rB Compare Compare Immediate CmpiCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 to Half-Word Extract Dynamic EXT16dEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC Half-Word Extract Static EXT16sEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itself Byte-Extract Dynamic EXT8dEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC Byte-Extract Static EXT8sEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itself Half-Word Fill FILL16FILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 Byte-Fill FILL8FILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 IF0 Equivalent to SKP1 InstructionIF0 %rA,IMM5 Equivalent to SKP0 Instruction IF1 IFRnz Equivalent to SKPRz InstructionIFRnz %rA IFRnz %o3 Equivalent to SKPRnz Instruction IFRz Conditionally Execute Next Instruction IFS Computed Jump JMPJMP %rA JMP %o7 return Word offset Load 32-bit Data From Memory Load 32-bit Data From Memory Pointer Addressing Mode LDPLDP %o3,%L2,3 Load %o3 from %L2 + LDS Lret Equivalent to JMP %o7Lret return Logical Shift Left LSLLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bits Logical Shift Left Immediate Lsli Logical Shift Right LSR Logical Shift Right Immediate Lsri Register-to-Register Move MOVMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0 Movhi Move Immediate Into High Half-WordMovhi %rA,IMM5 Movi Move ImmediateMovi %rA,IMM5 Multiply-Step MstepMstep %rA Mstep %r1 Multiply MUL %rAMUL %i5 Arithmetic Negation NEGNEG %rA NEG %o4 NOP Equivalent to MOV %g0, %g0NOP do nothing Logical Not NotNot %rA Not %o4 Or %rA,%rB Bitwise Logical orPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0 PFX PrefixPFX 3 affects next instruction Rdctl Read Control RegisterRdctl %rA Restore Caller’s Register Window Restore Restore restores caller’s register window RETEquivalent to JMP %i7 Rotate Left Through Carry RLC Rotate Right Through Carry RRC Save Save Caller’s Register WindowSave %sp,-IMM8 SEXT16 Sign Extend 16-bit ValueSEXT16 %rA SEXT8 Sign Extend 8-bit ValueSEXT8 %rA Skip If Register Bit Is SKP0 SKP1 %rA,IMM5 SKP1 Skip If Register Not Equal To SKPRnz SKPRz Skip If Register EqualsSKPRz %rA SKPRz %o3 Skps Skip On Condition CodeSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d Store 16-Bit Data To Memory Static Half-Word-Offset Address ST16sST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1 Store 8-Bit Data To Memory Computed Byte-Pointer Address ST8dST8d %rA,%r0 FILL8 %r0,%g3 Store 8-bit Data To Memory Static Byte-Offset Address ST8sMovi %g4,12 Mem%g4 + 36 + STP Store 32-bit Data To Memory Pointer Addressing Mode Store 32-bit Data To Memory Stack Addressing Mode STSSTS %sp,IMM8,%rA Store 16-bit Data To Memory Stack-Addressing Mode STS16sSTS16s %sp,IMM9,%r0 STS8s Store 8-bit Data To Memory Stack-Addressing ModeSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0 SUB SubtractSUB %rA,%rB Subi Subtract ImmediateSubi %rB,IMM5 Swap Unconditional Trap Trap Trap Return Tret Write Control Register Wrctl XOR Bitwise Logical Exclusive orXOR %rA,%rB 106 Numerics Index Index Index 110