Andn, PFX %hi16384 | Excalibur electronic A-MNL-NIOSPROG-01.1

32-Bit Instruction Set

ANDN

Bitwise Logical AND NOT

Operation:							Not preceded by PFX:
							RA ← RA & ~RB
							Preceded by PFX:
							RA ← RA & ~(0x00.00 : K : IMM5)
Assembler Syntax:							Not preceded by PFX:
							ANDN %rA,%rB
							Preceded by PFX:
							PFX %hi(const)
							ANDN %rA,%lo(const)
Example:							Not preceded by PFX:
							ANDN %g0,%g1 ; %g0 gets %g0 & ~%g1
							Preceded by PFX:
							PFX %hi(16384)
							ANDN %g0,%lo(16384) ; clear bit 14 of %g0
Description:							Not preceded by PFX:
							Logically-AND the individual bits in RA with the corresponding bits in the one’s-
							complement of RB; store the result in RA.
							Preceded by PFX:
							When prefixed, the RB operand is replaced by an immediate constant formed by
							concatenating the contents of the K-register (11 bits) with IMM5 (5 bits). This
							16-bit value is zero-extended to 32 bits, then bitwise-inverted and bitwise-ANDed
							with RA. The result is written back into RA.
Condition Codes:							Flags:
							N		V		Z		C

							∆		–		∆		–

							N: Result bit 31
							Z: Set if result is zero, cleared otherwise
Instruction Format:							RR, Ri5
Instruction Fields:							A = Register index of operand RA
							B = Register index of operand RB
							IMM5 = 5-bit immediate value
Not preceded by PFX (RR)
15	14	13		12		11		10			9		8		7	6	5		4	3	2	1	0

0	0	1		1		1		1							B						A

Preceded by PFX (Ri5)
15	14	13		12		11		10			9		8		7	6	5		4	3	2	1	0

0	0	1		1		1		1							IMM5						A

38	Altera Corporation

Image 50

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Bitwise Logical and not, PFX %hiconst Andn %rA,%loconst, PFX %hi16384

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date Description How to Contact Altera Information Type Access USA & Canada All Other Locations Visual Cue Meaning Typographic ConventionsConventions Courier type Altera Corporation Contents Bit Instruction Set Viii Contents Index 107 Altera Corporation List of Tables Xii Nios CPU Details Bit Nios CPU AudienceNios CPU Architecture General-Purpose Registers Register Groups Programmer’s Model Clrie Control Registers K RegisterProgram Counter Interrrupt Enable IE Condition Code Flags Condition Code Flags Typical 32-bit Nios CPU Program/Data Memory at Address Memory Access OverviewAddress Contents Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate Value Instructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFX Partial Width Register-Indirect Instructions Using Full Width Register-indirect AddressingFull Width Register-Indirect Instruction Address Register Data Register Instruction Address Register Full Width Register-Indirect with OffsetPartial Width Register-Indirect with Offset Offset Range without PFX Byte/Half-word Index Range Relative-Branch InstructionsInstruction Address Conditional Instructions Absolute-Jump InstructionsTrap Instructions Exception Handling Overview Exception Vector Table External Hardware Interrupt Sources Internal Exception Sources Register Window Overflow Direct Software Exceptions Trap Instructions Exception Processing Sequence Register Window Usage Return-Address Simple and Complex Exception Handlers Pipeline Implementation Pipeline Operation Branch Delay SlotsBR Branch Delay Slot Example Direct CWP Manipulation Notation Details Notation Meaning Instruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 2 USR0 Bit Major Opcode Table Sheet 3 MUL Operator Description Operation GNU Compiler/Assembler Pseudo-instructionsPsuedo-Instruction Altera Corporation Bit Instruction Set ABS %rA ABSAbsolute Value ABS %r6 ADD %rA,%rB ADDAdd Without Carry ADD %L3,%g0 ADD %g0 to %L3 Addi Add Immediate PFX %hiconst Bitwise Logical%rA,%rB PFX %hi16383 PFX %hiconst Andn %rA,%loconst AndnBitwise Logical and not PFX %hi16384 ASR Arithmetic Shift Right Asri Arithmetic Shift Right Immediate Bit Generate Bgen %rA,IMM5 Branch BR MainLoop BSR SendCharacter BSRBranch To Subroutine Call Call Subroutine Compare CMP %rA,%rB Cmpi & %rA,IMM5 CmpiCompare Immediate Cmpi %i3,24 compare %i3 to EXT16d %rA,%rB EXT16dHalf-Word Extract Dynamic LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16s %rA,IMM1 EXT16sHalf-Word Extract Static EXT16s %L3,1 %L3 gets upper short int of itself EXT8d %rA,%rB EXT8dByte-Extract Dynamic LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8s %rA,IMM2 EXT8sByte-Extract Static EXT8s %g6,3 %g6 gets the 3rd byte of itself FILL16 %r0,%rA FILL16Half-Word Fill FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL8 %r0,%rA FILL8Byte-Fill FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 IF0 %rA,IMM5 IF0Equivalent to SKP1 Instruction IF1 Equivalent to SKP0 Instruction IFRnz %rA IFRnz %o3 IFRnzEquivalent to SKPRz Instruction IFRz Equivalent to SKPRnz Instruction IFS Conditionally Execute Next Instruction JMP %rA JMPComputed Jump JMP %o7 return Load 32-bit Data From Memory Word offset LDP %o3,%L2,3 Load %o3 from %L2 + Load 32-bit Data From Memory Pointer Addressing ModeLDP LDS Lret return LretEquivalent to JMP %o7 LSL %rA,%rB LSLLogical Shift Left LSL %L3,%g0 Shift %L3 left by %g0 bits Lsli Logical Shift Left Immediate LSR Logical Shift Right Lsri Logical Shift Right Immediate MOV %rA,%rB MOVRegister-to-Register Move MOV %o0,%L3 copy %L3 into %o0 Movhi %rA,IMM5 MovhiMove Immediate Into High Half-Word Movi %rA,IMM5 MoviMove Immediate Mstep %rA MstepMultiply-Step Mstep %r1 MUL %i5 MultiplyMUL %rA NEG %rA NEGArithmetic Negation NEG %o4 NOP do nothing NOPEquivalent to MOV %g0, %g0 Not %rA NotLogical Not Not %o4 PFX %hiconst Or %ra,%loconst Bitwise Logical orOr %rA,%rB Or %i0,%i1 or %i1 into %i0 PFX 3 affects next instruction PFXPrefix Rdctl %rA RdctlRead Control Register Restore Restore Caller’s Register Window Equivalent to JMP %i7 Restore restores caller’s register windowRET RLC Rotate Left Through Carry RRC Rotate Right Through Carry Save %sp,-IMM8 SaveSave Caller’s Register Window SEXT16 %rA SEXT16Sign Extend 16-bit Value SEXT8 %rA SEXT8Sign Extend 8-bit Value SKP0 Skip If Register Bit Is SKP1 SKP1 %rA,IMM5 SKPRnz Skip If Register Not Equal To SKPRz %rA SKPRz %o3 SKPRzSkip If Register Equals Skps ccIMM4 Skps ccne SkpsSkip On Condition Code Store 32-bit Data To Memory ST16d ST16s %rA,%r0,IMM1 ST16sStore 16-Bit Data To Memory Static Half-Word-Offset Address PFX Y ST16s %rA,%r0,Y 1 ST8d %rA,%r0 ST8dStore 8-Bit Data To Memory Computed Byte-Pointer Address FILL8 %r0,%g3 Movi %g4,12 ST8sStore 8-bit Data To Memory Static Byte-Offset Address Mem%g4 + 36 + Store 32-bit Data To Memory Pointer Addressing Mode STP STS %sp,IMM8,%rA Store 32-bit Data To Memory Stack Addressing ModeSTS STS16s %sp,IMM9,%r0 Store 16-bit Data To Memory Stack-Addressing ModeSTS16s STS8s %sp,IMM10,%r0 Store 8-bit Data To Memory Stack-Addressing ModeSTS8s FILL8 %r0,%rX STS8s %sp,Y,%r0 SUB %rA,%rB SUBSubtract Subi %rB,IMM5 SubiSubtract Immediate Swap Trap Unconditional Trap Tret Trap Return Wrctl Write Control Register XOR %rA,%rB XORBitwise Logical Exclusive or 106 Index Numerics Index Index 110