Overview

Interrrupt Enable (IE)

IE is the interrupt enable bit. When IE=1, it enables external interrupts and internal exceptions. IE=0 disables external interrupts and exceptions. Software TRAP instructions will still execute normally even when IE=0. Note that IE can be set directly without affecting the rest of the STATUS register by writing to the SET_IE (%ctl9) and CLR_IE (%ctl8) control registers. When the CPU is reset, IE is set to 0 (interrupts disabled).

Interrupt Priority (IPRI)

IPRI contains the current running interrupt priority. When an exception is processed, the IPRI value is set to the exception number. See “Exceptions” on page 16 for more information. For external hardware interrupts, the IPRI value is set directly from the 6-bit hardware interrupt number. For TRAP instructions, the IPRI field is set directly from the IMM6 field of the instruction. For internal exceptions, the IPRI field is set from the pre-defined 6-bit exception number.

A hardware interrupt is not processed if its internal number is greater than or equal to IPRI or IE=0. A TRAP instruction is processed unconditionally. When the CPU is reset, IPRI is set to 63 (lowest-priority). IPRI disables interrupts above a certain number. For example, if IPRI is 3, then interrupts 0, 1 and 2 will be processed, but all others (interrupts 3-63) are disabled.

Current Window Pointer (CWP)

CWP points to the base of the sliding register window in the general- purpose register file. Incrementing CWP moves the register window up 16 registers. Decrementing CWP moves the register window down 16 registers. CWP is decremented by SAVE instructions and incremented by RESTORE instructions.

Only specialized system software such as register window-management facilities should directly write values to CWP through WRCTL. Software will normally modify CWP by using SAVE and RESTORE instructions.

When the CPU is reset, CWP is set to the largest valid value, HI_LIMIT. This means in a 256 register file size, there will be 16 register windows. After reset, the WVALID register (%ct12) is set to 0x01C1, i.e., LO_LIMIT

=1 and HI_ LIMIT =14. See “WVALID (%ctl2)” on page 6 for more information.

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Overview

Altera Corporation

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Interrrupt Enable IE