Excalibur electronic A-MNL-NIOSPROG-01.1 manual

Overview

Table 17. 32-bit Major Opcode Table (Sheet 1 of 3)

Opcode	Mnemonic	Format	Summary

000000	ADD	RR	RA ← RA + RB
			Flags affected: N, V, C, Z

000001	ADDI	Ri5	RA ← RA + (0×00.00 : K : IMM5)
			Flags affected: N, V, C, Z

000010	SUB	RR	RA ← RA – RB
			Flags affected: N, V, C, Z

000011	SUBI	Ri5	RA ← RA – (0×00.00 : K : IMM5)
			Flags affected: N, V, C, Z

000100	CMP	RR	∅ ← RA – RB
			Flags affected: N, V, C, Z

000101	CMPI	Ri5	∅ ← RA – (0×00.00 : K : IMM5)
			Flags affected: N, V, C, Z

000110	LSL	RR	RA ← (RA << RB [4..0]),
			Zero-fill from right

000111	LSLI	Ri5	RA ← (RA << IMM5),
			Zero-fill from right

001000	LSR	RR	RA ← (RA >> RB [4..0]),
			Zero-fill from left

001001	LSRI	Ri5	RA ← (R >> IMM5),
			Zero-fill form left

001010	ASR	RR	RA ← (RA >> RB [4..0]),
			Fill from left with RA[31]

001011	ASRI	Ri5	RA ← (RA >> IMM5),
			Fill from left with RA[31]

001100	MOV	RR	RA ← RB

001101	MOVI	Ri5	RA ← (0×00.00 : K : IMM5)
001110	AND	RR	RA ← RA & {RB, (0×00.00 : K : IMM5)}
		Ri5	Flags affected: N, Z

001111	ANDN	RR,	RA ← RA & ~({RB, (0×00.00 : K : IMM5)})
		Ri5	Flags affected: N, Z

010000	OR	RR,	RA ← RA {RB, (0×00.00 : K : IMM5)}
		Ri5	Flags affected: N, Z

010001	XOR	RR,	RA ← RA ⊕ {RB, (0×00.00 : K : IMM5)}
		Ri5	Flags affected: N, Z

010010	BGEN	Ri5	RA ← 2IMM5
010011	EXT8d	RR	RA ← (0×00.00.00 : bnRA) where n = RB[1..0]
010100	SKP0	Ri5	Skip next instruction if: (RA [IMM5] == 0)

010101	SKP1	Ri5	Skip next instruction if: (RA [IMM5] == 1)

010110	LD	RR	RA ← Mem32 [align32( RB + (σ(K) × 4))]

28	Altera Corporation

Image 40

Excalibur electronic A-MNL-NIOSPROG-01.1 manual Bit Major Opcode Table Sheet 1, Opcode Mnemonic Format Summary

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date Description How to Contact Altera Information Type Access USA & Canada All Other Locations Typographic Conventions ConventionsVisual Cue Meaning Courier type Altera Corporation Contents Bit Instruction Set Viii Contents Index 107 Altera Corporation List of Tables Xii Nios CPU Architecture AudienceNios CPU Details Bit Nios CPU General-Purpose Registers Register Groups Programmer’s Model Clrie Program Counter K RegisterControl Registers Interrrupt Enable IE Condition Code Flags Condition Code Flags Address Contents Memory Access OverviewTypical 32-bit Nios CPU Program/Data Memory at Address Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate Value Instructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using Full Width Register-indirect Addressing Full Width Register-IndirectPartial Width Register-Indirect Instruction Address Register Data Register Full Width Register-Indirect with Offset Partial Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFX Instruction Address Relative-Branch InstructionsByte/Half-word Index Range Trap Instructions Absolute-Jump InstructionsConditional Instructions Exception Handling Overview Exception Vector Table External Hardware Interrupt Sources Internal Exception Sources Register Window Overflow Direct Software Exceptions Trap Instructions Exception Processing Sequence Register Window Usage Return-Address Simple and Complex Exception Handlers Pipeline Implementation BR Branch Delay Slot Example Branch Delay SlotsPipeline Operation Direct CWP Manipulation Notation Details Notation Meaning Instruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 2 USR0 Bit Major Opcode Table Sheet 3 MUL Psuedo-Instruction GNU Compiler/Assembler Pseudo-instructionsOperator Description Operation Altera Corporation Bit Instruction Set ABS Absolute ValueABS %rA ABS %r6 ADD Add Without CarryADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3 Addi Add Immediate Bitwise Logical %rA,%rBPFX %hiconst PFX %hi16383 Andn Bitwise Logical and notPFX %hiconst Andn %rA,%loconst PFX %hi16384 ASR Arithmetic Shift Right Asri Arithmetic Shift Right Immediate Bit Generate Bgen %rA,IMM5 Branch BR MainLoop Branch To Subroutine BSRBSR SendCharacter Call Call Subroutine Compare CMP %rA,%rB Cmpi Compare ImmediateCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 to EXT16d Half-Word Extract DynamicEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16s Half-Word Extract StaticEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itself EXT8d Byte-Extract DynamicEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8s Byte-Extract StaticEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itself FILL16 Half-Word FillFILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL8 Byte-FillFILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 Equivalent to SKP1 Instruction IF0IF0 %rA,IMM5 IF1 Equivalent to SKP0 Instruction Equivalent to SKPRz Instruction IFRnzIFRnz %rA IFRnz %o3 IFRz Equivalent to SKPRnz Instruction IFS Conditionally Execute Next Instruction JMP Computed JumpJMP %rA JMP %o7 return Load 32-bit Data From Memory Word offset LDP Load 32-bit Data From Memory Pointer Addressing ModeLDP %o3,%L2,3 Load %o3 from %L2 + LDS Equivalent to JMP %o7 LretLret return LSL Logical Shift LeftLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bits Lsli Logical Shift Left Immediate LSR Logical Shift Right Lsri Logical Shift Right Immediate MOV Register-to-Register MoveMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0 Move Immediate Into High Half-Word MovhiMovhi %rA,IMM5 Move Immediate MoviMovi %rA,IMM5 Mstep Multiply-StepMstep %rA Mstep %r1 MUL %rA MultiplyMUL %i5 NEG Arithmetic NegationNEG %rA NEG %o4 Equivalent to MOV %g0, %g0 NOPNOP do nothing Not Logical NotNot %rA Not %o4 Bitwise Logical or Or %rA,%rBPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0 Prefix PFXPFX 3 affects next instruction Read Control Register RdctlRdctl %rA Restore Restore Caller’s Register Window RET Restore restores caller’s register windowEquivalent to JMP %i7 RLC Rotate Left Through Carry RRC Rotate Right Through Carry Save Caller’s Register Window SaveSave %sp,-IMM8 Sign Extend 16-bit Value SEXT16SEXT16 %rA Sign Extend 8-bit Value SEXT8SEXT8 %rA SKP0 Skip If Register Bit Is SKP1 SKP1 %rA,IMM5 SKPRnz Skip If Register Not Equal To Skip If Register Equals SKPRzSKPRz %rA SKPRz %o3 Skip On Condition Code SkpsSkps ccIMM4 Skps ccne Store 32-bit Data To Memory ST16d ST16s Store 16-Bit Data To Memory Static Half-Word-Offset AddressST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1 ST8d Store 8-Bit Data To Memory Computed Byte-Pointer AddressST8d %rA,%r0 FILL8 %r0,%g3 ST8s Store 8-bit Data To Memory Static Byte-Offset AddressMovi %g4,12 Mem%g4 + 36 + Store 32-bit Data To Memory Pointer Addressing Mode STP STS Store 32-bit Data To Memory Stack Addressing ModeSTS %sp,IMM8,%rA STS16s Store 16-bit Data To Memory Stack-Addressing ModeSTS16s %sp,IMM9,%r0 Store 8-bit Data To Memory Stack-Addressing Mode STS8sSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0 Subtract SUBSUB %rA,%rB Subtract Immediate SubiSubi %rB,IMM5 Swap Trap Unconditional Trap Tret Trap Return Wrctl Write Control Register Bitwise Logical Exclusive or XORXOR %rA,%rB 106 Index Numerics Index Index 110