Bit Instruction Set | Excalibur electronic A-MNL-NIOSPROG-01.1

Contents
32-Bit Instruction Set	33
ABS	34
ADD	35
ADDI	36
AND	37
ANDN	38
ASR	39
ASRI	40
BGEN	41
BR	42
BSR	43
CALL	44
CMP	45
CMPI	46
EXT16d	47
EXT16s	48
EXT8d	49
EXT8s	50
FILL16	51
FILL8	52
IF0	53
IF1	54
IFRnz	55
IFRz	56
IFS	57
JMP	58
LD	59
LDP	60
LDS	61
LRET	62
LSL	63
LSLI	64
LSR	65
LSRI	66
MOV	67
MOVHI	68
MOVI	69
MSTEP	70
MUL	71
NEG	72
NOP	73
NOT	74
OR	75
PFX	76
RDCTL	77
RESTORE	78

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Excalibur electronic A-MNL-NIOSPROG-01.1 manual Bit Instruction Set, Viii

Contents

Nios Embedded Processor Nios Embedded Processor Programmer’s Reference Manual Revision History Revision Date Description How to Contact Altera Information Type Access USA & Canada All Other Locations Typographic Conventions ConventionsVisual Cue Meaning Courier type Altera Corporation Contents Bit Instruction Set Viii Contents Index 107 Altera Corporation List of Tables Xii Nios CPU Details Bit Nios CPU AudienceNios CPU Architecture General-Purpose Registers Register Groups Programmer’s Model Clrie Control Registers K RegisterProgram Counter Interrrupt Enable IE Condition Code Flags Condition Code Flags Typical 32-bit Nios CPU Program/Data Memory at Address Memory Access OverviewAddress Contents Code Example 1 Reading a Single Byte from Memory Writing to Memory or Peripherals Addressing Modes Bit Immediate Value Instructions Using 5/16-bit Immediate Values Code Example 3 The Addi Instruction Used with/without a PFX Instructions Using Full Width Register-indirect Addressing Full Width Register-IndirectPartial Width Register-Indirect Instruction Address Register Data Register Full Width Register-Indirect with Offset Partial Width Register-Indirect with OffsetInstruction Address Register Offset Range without PFX Byte/Half-word Index Range Relative-Branch InstructionsInstruction Address Conditional Instructions Absolute-Jump InstructionsTrap Instructions Exception Handling Overview Exception Vector Table External Hardware Interrupt Sources Internal Exception Sources Register Window Overflow Direct Software Exceptions Trap Instructions Exception Processing Sequence Register Window Usage Return-Address Simple and Complex Exception Handlers Pipeline Implementation Pipeline Operation Branch Delay SlotsBR Branch Delay Slot Example Direct CWP Manipulation Notation Details Notation Meaning Instruction Format Sheet 1 Instruction Format Sheet 2 Bit Major Opcode Table Sheet 1 Opcode Mnemonic Format Summary Bit Major Opcode Table Sheet 2 USR0 Bit Major Opcode Table Sheet 3 MUL Operator Description Operation GNU Compiler/Assembler Pseudo-instructionsPsuedo-Instruction Altera Corporation Bit Instruction Set ABS Absolute ValueABS %rA ABS %r6 ADD Add Without CarryADD %rA,%rB ADD %L3,%g0 ADD %g0 to %L3 Addi Add Immediate Bitwise Logical %rA,%rBPFX %hiconst PFX %hi16383 Andn Bitwise Logical and notPFX %hiconst Andn %rA,%loconst PFX %hi16384 ASR Arithmetic Shift Right Asri Arithmetic Shift Right Immediate Bit Generate Bgen %rA,IMM5 Branch BR MainLoop BSR SendCharacter BSRBranch To Subroutine Call Call Subroutine Compare CMP %rA,%rB Cmpi Compare ImmediateCmpi & %rA,IMM5 Cmpi %i3,24 compare %i3 to EXT16d Half-Word Extract DynamicEXT16d %rA,%rB LD %i3,%i4 get 32 bits from %i4 & 0xFF.FF.FF.FC EXT16s Half-Word Extract StaticEXT16s %rA,IMM1 EXT16s %L3,1 %L3 gets upper short int of itself EXT8d Byte-Extract DynamicEXT8d %rA,%rB LD %g4,%i0 get 32 bits from %i0 & 0xFF.FF.FF.FC EXT8s Byte-Extract StaticEXT8s %rA,IMM2 EXT8s %g6,3 %g6 gets the 3rd byte of itself FILL16 Half-Word FillFILL16 %r0,%rA FILL16 %r0,%i3 %r0 gets 2 copies of %i30..15 FILL8 Byte-FillFILL8 %r0,%rA FILL8 %r0,%o3 %r0 gets 4 copies of %o30..7 IF0 %rA,IMM5 IF0Equivalent to SKP1 Instruction IF1 Equivalent to SKP0 Instruction IFRnz %rA IFRnz %o3 IFRnzEquivalent to SKPRz Instruction IFRz Equivalent to SKPRnz Instruction IFS Conditionally Execute Next Instruction JMP Computed JumpJMP %rA JMP %o7 return Load 32-bit Data From Memory Word offset LDP %o3,%L2,3 Load %o3 from %L2 + Load 32-bit Data From Memory Pointer Addressing ModeLDP LDS Lret return LretEquivalent to JMP %o7 LSL Logical Shift LeftLSL %rA,%rB LSL %L3,%g0 Shift %L3 left by %g0 bits Lsli Logical Shift Left Immediate LSR Logical Shift Right Lsri Logical Shift Right Immediate MOV Register-to-Register MoveMOV %rA,%rB MOV %o0,%L3 copy %L3 into %o0 Movhi %rA,IMM5 MovhiMove Immediate Into High Half-Word Movi %rA,IMM5 MoviMove Immediate Mstep Multiply-StepMstep %rA Mstep %r1 MUL %i5 MultiplyMUL %rA NEG Arithmetic NegationNEG %rA NEG %o4 NOP do nothing NOPEquivalent to MOV %g0, %g0 Not Logical NotNot %rA Not %o4 Bitwise Logical or Or %rA,%rBPFX %hiconst Or %ra,%loconst Or %i0,%i1 or %i1 into %i0 PFX 3 affects next instruction PFXPrefix Rdctl %rA RdctlRead Control Register Restore Restore Caller’s Register Window Equivalent to JMP %i7 Restore restores caller’s register windowRET RLC Rotate Left Through Carry RRC Rotate Right Through Carry Save %sp,-IMM8 SaveSave Caller’s Register Window SEXT16 %rA SEXT16Sign Extend 16-bit Value SEXT8 %rA SEXT8Sign Extend 8-bit Value SKP0 Skip If Register Bit Is SKP1 SKP1 %rA,IMM5 SKPRnz Skip If Register Not Equal To SKPRz %rA SKPRz %o3 SKPRzSkip If Register Equals Skps ccIMM4 Skps ccne SkpsSkip On Condition Code Store 32-bit Data To Memory ST16d ST16s Store 16-Bit Data To Memory Static Half-Word-Offset AddressST16s %rA,%r0,IMM1 PFX Y ST16s %rA,%r0,Y 1 ST8d Store 8-Bit Data To Memory Computed Byte-Pointer AddressST8d %rA,%r0 FILL8 %r0,%g3 ST8s Store 8-bit Data To Memory Static Byte-Offset AddressMovi %g4,12 Mem%g4 + 36 + Store 32-bit Data To Memory Pointer Addressing Mode STP STS %sp,IMM8,%rA Store 32-bit Data To Memory Stack Addressing ModeSTS STS16s %sp,IMM9,%r0 Store 16-bit Data To Memory Stack-Addressing ModeSTS16s Store 8-bit Data To Memory Stack-Addressing Mode STS8sSTS8s %sp,IMM10,%r0 FILL8 %r0,%rX STS8s %sp,Y,%r0 SUB %rA,%rB SUBSubtract Subi %rB,IMM5 SubiSubtract Immediate Swap Trap Unconditional Trap Tret Trap Return Wrctl Write Control Register XOR %rA,%rB XORBitwise Logical Exclusive or 106 Index Numerics Index Index 110

32-Bit Instruction Set

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Altera Corporation