Power Management, SMBus Interface, Introduction | Intel 41110

Introduction

•Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transaction.

•Tunable inbound read prefetch algorithm for PCI MRM/MRL commands

•Local initialization via SMBus

•Secondary side initialization via Type 0 configuration cycles.

2.3Power Management

•Support for PCI Express Active State Power Management (ASPM) L0s link state

•Support for PCI PM 1.1 compatible D0, D3hot and D3cold device power states

•Support for PME# event propagation on behalf of PCI devices

2.4SMBus Interface

•Compatible with System Management Bus Specification, Revision 2.0

•Slave mode operation only.

•Full read/write access to all configuration registers

2.4.1SMBus for configuration register initialization

•Support for local initialization of the configuration registers can be implemented using a microcontroller via SMB. Figure 1shows this SMBus and the data transfer that occurs between the 41110 and the microcontroller.

•Configuration Register information is stored internally in a microcontroller and the information is transferred to the product via System Managed Bus (SMBus) protocols when the device receives power or reset.

•The requirements of the microcontroller are as follows:

—Supports I2C and SMBus Protocols

—Has at least 256 Byte of internal EEprom space

—To facilitate this programming on the Customer Reference Board a Microchip part PIC16F876A was used.

—Code space: estimated code size is ~2K words of program space and 32 words of RAM

10	Intel® 41110 Serial to Parallel PCI Bridge Design Guide

Image 10

Intel 41110 manual Power Management, SMBus Interface, SMBus for configuration register initialization, Introduction

Contents

Intel 41110 Serial to Parallel PCI Bridge Design Guide Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Contents Revision History Date Revision Description March 001 Initial release Terminology and Definitions Sheet 1 About This DocumentTerminology and Definitions Term Definition About This Document Terminology and Definitions Sheet 2 PCI-X Interface Features PCI Express Interface FeaturesIntroduction2 SMBus Interface Power ManagementSMBus for configuration register initialization Introduction Microcontroller Block Diagram Microcontroller Connections to Jtag Related Documents Block Diagram Intel 41110 Serial to Parallel PCI Bridge Applications Adapter Card Block Diagram Package Specification Package Information Bridge Package Dimensions Side View Package Information Power Plane Layout 41110 Decoupling Guidelines Power Plane Layout 41110 Split Voltage PlanesDecoupling Guidelines 300 PCI ARST# and PERST# Timing Requirements Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing Guidelines Trace Impedance Power Distribution and DecouplingDecoupling Differential Impedance Cross Section of Differential Trace Adapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card Stackup Interrupts AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines INTx Routing Table PCI-X Layout Guidelines PCI ArbitrationInterrupt Routing for Devices Behind a Bridge Interrupt Binding for Devices Behind a Bridge PCI General Layout Guidelines PCI Resistor Compensation PCI Pullup Resistors Not Required PCI-X SignalsPCI Clock Layout Guidelines PCI/PCI-X Frequency/Mode Straps PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing Guidelines 41110 Layout Analysis PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing Recommendations PCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing Recommendations PCI 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing Recommendations PCI Express Layout General recommendations PCI Express Layout PCI-Express Layout GuidelinesAdapter Card Layout Guidelines Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank 10.1 41110 Analog Voltage Filters ConfigCircuit Implementations Circuit Implementations PCI Analog Voltage Filters PCI Express Analog Voltage Filter Bandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter Circuit SM Bus SMBUs Address ConfigurationBit Value This page intentionally left blank Board Stack-up Layer Type Thickness Copper WeightCustomer Reference Boards CRB Board Stackup Sheet 1 Customer Reference Boards MaterialImpedance CRB Board Stackup Sheet 2 Board Outline Mechanical Outline This page intentionally left blank Signals Recommendations Reason/Impact Design Guide ChecklistPCI Express Interface Signals PERCOMP10 Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1 PCI/PCI-X Interface Signals Sheet 2 Miscellaneous Signals SMBus Interface Signals Recommendations Reason/Impact Reset Pins Ballout Pin Name Usage Power and Ground Signals Signal Recommendations Reason/Impact Jtag Signals This page intentionally left blank