Adapter Card Routing Recommendations Sheet 2 | Intel 41110 specs

PCI Express Layout

Table 15. Adapter Card Routing Recommendations (Sheet 2 of 2)

Receive Trace Length (Card
edge finger to 41110 receiver	1.0” min - 6.0” max
pin
Length Matching	Total allowable intra-pair length mis-match must not exceed 25 mils. Each
Length Matching	routing segment should be matched as close as possible. Total skew across all
Requirements:	lanes must be less than 20 ns. See the PCI-Express Desktop Design Guidelines
	for additional routing requirements

Number of vias	4 max

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Intel 41110 manual Adapter Card Routing Recommendations Sheet 2

Contents

Design Guide Intel 41110 Serial to Parallel PCI Bridge Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables Figures Contents Date Revision Description March 001 Initial release Revision History Term Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1 Terminology and Definitions Sheet 2 About This Document PCI-X Interface Features PCI Express Interface FeaturesIntroduction2 Introduction Power ManagementSMBus for configuration register initialization SMBus Interface Microcontroller Connections to Microcontroller Block Diagram Related Documents Jtag Intel 41110 Serial to Parallel PCI Bridge Applications Block Diagram Adapter Card Block Diagram Package Information Package Specification Package Information Bridge Package Dimensions Side View 41110 Decoupling Guidelines Power Plane Layout Power Plane Layout 300 Split Voltage PlanesDecoupling Guidelines 41110 PCI ARST# and PERST# Timing Requirements Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI Considerations Trace Impedance Power Distribution and DecouplingDecoupling Cross Section of Differential Trace Differential Impedance Adapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout Guidelines INTx Routing Table AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines Interrupts Interrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout Guidelines PCI Resistor Compensation PCI General Layout Guidelines PCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Clock Layout Guidelines PCI Pullup Resistors Not Required PCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary 41110 Layout Analysis PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHz PCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 66 MHz Embedded Topology PCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode Topology General recommendations PCI Express Layout Adapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express Layout Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations ConfigCircuit Implementations 10.1 41110 Analog Voltage Filters PCI Express Analog Voltage Filter PCI Analog Voltage Filters PCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage Filter Bandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation Pins SM Bus SMBUs Address ConfigurationBit Value This page intentionally left blank CRB Board Stackup Sheet 1 Layer Type Thickness Copper WeightCustomer Reference Boards Board Stack-up CRB Board Stackup Sheet 2 MaterialImpedance Customer Reference Boards Mechanical Outline Board Outline This page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/Impact PCI/PCI-X Interface Signals Sheet 1 Design Guide Checklist Miscellaneous Signals PCI/PCI-X Interface Signals Sheet 2 Recommendations Reason/Impact SMBus Interface Signals Ballout Pin Name Usage Reset Pins Signal Recommendations Reason/Impact Power and Ground Signals Jtag Signals This page intentionally left blank