Intel® 41110 Serial to Parallel PCI Bridge Design Guide 9
Introduction 2The Intel® 41110 Serial to Parallel PCI Bridge integrates a PCI Express-to-PCI bridge. The bridge
follows the PCI-to-PCI Bridge programming model. The PCI Express port is compliant to the PCI
Express Specification, Revision1.0. The PCI bus interface is fully compliant to the PCI Local Bus
Specification, Revision 2.3.
2.1 PCI Express Interface Features
•PCI Express Specification, Revision1.0b compliant.
•Support for single x8, single x4 or single x1 PCI Express operation.
•64-bit addressing support.
•32-bit CRC (cyclic redundancy checking) covering all transmitted data packets.
•16-bit CRC on all link message information.
•Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/s.
•Maximum realized bandwidth on PCI Express interface is 2GB/s (in x8 mode) in each
direction simultaneously, for an aggregate of 4GB/s.
2.2 PCI-X Interface Features
•PCI Local Bus Specification, Revision 2.3 compliant.
•PCI-to-PCI Bridge Specification, Revision 1.1 compliant.
•PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a compliant.
•64-bit 66 MHz, 3.3 V, NOT 5V tolerant.
•On Die Termination (ODT) with 8.2KΩ pull-up to 3.3V for PCI signals.
•Six external REQ/GNT Pairs for internal arbiter on the PCIX bus segment respectively.
•Programmable bus parking on either the last agent or always on Intel® 41110 Se rial to Parallel
PCI Bridge.
•2-level programmable round-robin internal arbiter with Multi-Transaction Timer (MTT)
•External PCI clock-feed support for asynchronous primary and secondary domain operation.
•64-bit addressing for upstream and downstream transactions
•Downstream LOCK# support.
•No upstream LOCK# support.
•PCI fast Back-to-Back capable as target.
•Up to four active and four pending upstream memory read transactions