PCI 33 MHz Embedded Mode Topology | Intel 41110 manual

PCI-X Layout Guidelines

8.6.5PCI 33 MHz Embedded Mode Topology

Figure 21 and Table 14 provide routing details for a topology with an embedded PCI 33 MHz design.

Figure 21. PCI 33 MHz Embedded Mode Routing Topology

	EM1	EM3	EM5	EM7	EM9
	TL EM1	TL EM3	TL EM5	TL EM7	TL EM9
TL1	TL2	TL3	TL4		TL5
	TL EM2	TL EM4	TL EM6	TL EM8	TL EM10
	EM2	EM4	EM6	EM8	EM10
					B2723 -01

Table 14.	PCI 33 MHz Embedded Routing Recommendations

	Parameter	Routing Guideline for Lower AD Bus

	Reference Plane	Route over an unbroken ground plane

	Board Impedance	60 Ω +/- 15%

	Stripline Trace Spacing	12 mils, edge to edge

	Microstrip Trace Spacing	18 mils edge to edge

	Group Spacing	Spacing from other groups: 25 mils min, edge to edge

	Breakout	5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils.

	Trace Length 1 TL1: From
	41110 signal Ball to first	5.0” max
	junction

	Trace Length TL2 to TL5 -	0.5” min - 3.5” max
	between junctions	0.5” min - 3.5” max
	between junctions
	Trace Length TL_EM1 to
	TL_EM10 from junction to	2.0” min - 3.0” max
	embedded devices

	Length Matching	Clocks coming from the clock driver must be length matched to within 25 mils.
	Requirements
	Requirements

40	Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Intel 41110 manual PCI 33 MHz Embedded Mode Topology, PCI 33 MHz Embedded Routing Recommendations

Contents

Intel 41110 Serial to Parallel PCI Bridge Design Guide Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Contents Revision History Date Revision Description March 001 Initial release About This Document Terminology and DefinitionsTerminology and Definitions Sheet 1 Term Definition About This Document Terminology and Definitions Sheet 2 PCI-X Interface Features PCI Express Interface FeaturesIntroduction2 Power Management SMBus for configuration register initializationSMBus Interface Introduction Microcontroller Block Diagram Microcontroller Connections to Jtag Related Documents Block Diagram Intel 41110 Serial to Parallel PCI Bridge Applications Adapter Card Block Diagram Package Specification Package Information Bridge Package Dimensions Side View Package Information Power Plane Layout 41110 Decoupling Guidelines Power Plane Layout Split Voltage Planes Decoupling Guidelines41110 300 PCI ARST# and PERST# Timing Requirements Reset and Power Timing Considerations5VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk EMI Considerations General Routing Guidelines Trace Impedance Power Distribution and DecouplingDecoupling Differential Impedance Cross Section of Differential Trace Adapter Card Topology Board Layout GuidelinesAdapter Card Stack Up, Microstrip and Stripline Board Layout Guidelines Adapter Card Stackup AINT# Interrupt Pins PCI Express INTx Message PCI-X Layout GuidelinesInterrupts INTx Routing Table PCI Arbitration Interrupt Routing for Devices Behind a BridgePCI-X Layout Guidelines Interrupt Binding for Devices Behind a Bridge PCI General Layout Guidelines PCI Resistor Compensation PCI-X Signals PCI Clock Layout GuidelinesPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode Straps PCI Clock Distribution and Matching Requirements PCI-X Clock Layout Requirements Summary Parameter Routing Guidelines 41110 Layout Analysis PCI-X Topology Layout GuidelinesPCI-X Slot Guidelines Embedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 133 MHzParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Embedded PCI-X 100 MHz Routing Recommendations PCI-X 66 MHz Embedded Topology PCI-X 66 MHz Embedded Routing Recommendations PCI 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 33 MHz Embedded Mode Topology PCI 33 MHz Embedded Routing Recommendations PCI Express Layout General recommendations PCI-Express Layout Guidelines Adapter Card Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Config Circuit Implementations10.1 41110 Analog Voltage Filters Circuit Implementations PCI Analog Voltage Filters PCI Express Analog Voltage Filter Bandgap Analog Voltage Filter PCI Express Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation Pins Bandgap Analog Voltage Filter Circuit SM Bus SMBUs Address ConfigurationBit Value This page intentionally left blank Layer Type Thickness Copper Weight Customer Reference BoardsBoard Stack-up CRB Board Stackup Sheet 1 Material ImpedanceCustomer Reference Boards CRB Board Stackup Sheet 2 Board Outline Mechanical Outline This page intentionally left blank Design Guide Checklist PCI Express Interface SignalsSignals Recommendations Reason/Impact PERCOMP10 Design Guide Checklist PCI/PCI-X Interface Signals Sheet 1 PCI/PCI-X Interface Signals Sheet 2 Miscellaneous Signals SMBus Interface Signals Recommendations Reason/Impact Reset Pins Ballout Pin Name Usage Power and Ground Signals Signal Recommendations Reason/Impact Jtag Signals This page intentionally left blank