Intel 41110 8.4 PCI Clock Layout Guidelines

32 Intel® 41110 Serial to Parallel PCI Bridge Design Guide

PCI-X Layout Guidelines

Table 7. PCI/PCI-X Frequency/Mode Straps

Note: All signals sampled on the rising edge of PERST#.

8.3.1 PCI Pullup Resistors Not Required

PCI control signals on the 41110 do NOT require pu llup resi stor s on the adapt er card to ens ure that

they contain stable values when no agent is actively driving the bus. These include:

A_ACK64#, A_AD[63:32], A_CBE#[7:4], A_DEVSEL#, A_FRAME#, A_INTA#, A_INTB#,

A_INTC#, A_INTD#, A_IRDY#, A_PERR#, A_PAR, A_GNT#[5:0], A_REQ#[5:0], A_LOCK#,

A_PAR64, A_REQ64#, A_SERR#, A_STOP#, and A_TRDY#

8.4 PCI Clock Layout Guidelines

The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a compliant, allows a

maximum of 0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz and

133 MHz. A typical PCI-X application may require separate clock point-to-point connections

Table 6. PCI-X Signals

Timing Critical Signals

A PCI Bus Segment:

A_ACK64#, A_AD[63:0], A_CBE_[7:0]#, A_DEVSEL#, A_FRAME#,

A_GNT_[5:0]#, A_IRDY#, A_LOCK#, A_PAR64, A_REQ64#, A_REQ_[5:0]#,

A_STOP#, A_TRDY#, A_CLKO[6:0], A_CLKI

Reset Signals A PCI Bus Segment:

A_RST#, A_PME#

Non Timing Critical

Signals A PCI Bus Segment:

A_133EN, A_IRQ[15:0]#, A_M66EN, A_PCIXCAP, A_PERR#, A_SERR#

A_PCIXCAP A_M66EN A_133EN(on

board)

Bus

Mode/

Freq

00XPCI 33

01XPCI 66

PCI-X 66MHz cards connect this

signal to ground through a 10KΩ

±5% resistor in parallel with a

0.01uF ±10% capacitor.

XXPCI-X 66

PCI-X 133 MHz cards connect

PCIXCAP to ground through a

0.01uF ±10% capacitor. X0PCI-X 100

PCI-X 133 MHz cards connect

PCIXCAP to ground through a

0.01uF ±10% capacitor. X1PCI-X 133

Contents

Main ii Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Figures Tables Page Page About This Document 1 1.1 Terminology and Definitions About This Document Table 1. Terminology and Definitions (Sheet 2 of 2) Introduction 2 2.1 PCI Express Interface Features 2.2 PCI-X Interface Features 2.3 Power Management 2.4 SMBus Interface 2.4.1 SMBus for configuration register initialization Page 2.5 JTAG 2.6 Related Documents Page Page Package Information 3 3.1 Package Specification Package Information Figure 6. 41110 Bridge Package Dimensions (Side View) Power Plane Layout 4 4.1 41110 Decoupling Guidelines Page Power Plane Layout Table 2. 41110 Decoupling Guidelines 4.2 Split Voltage Planes There are two 1.5V voltage planes that supply power to the 41110: Page 41110 Reset and Power Timing Considerations 5 5.1 A_RST# and PERST# Timing Requirements 5.2 VCC15 and VCC33 Voltage Requirements Page General Routing Guidelines 6 6.1 General Routing Guidelines 6.2 Crosstalk 6.3 EMI Considerations 6.4 Power Distribution and Decoupling 6.4.1 Decoupling 6.5 Trace Impedance 6.5.1 Differential Impedance Z Z11 Z12 Z21 Z22 = Board Layout Guidelines 7 7.1 Adapter Card Topology Page PCI-X Layout Guidelines 8 8.1 Interrupts 8.1.1 Interrupt Routing for Devices Behind a Bridge 8.2 PCI Arbitration 8.2.1 PCI Resistor Compensation 8.3 PCI General Layout Guidelines 8.3.1 PCI Pullup Resistors Not Required 8.4 PCI Clock Layout Guidelines Page Table 8. PCI-X Clock Layout Requirements Summary 8.5 PCI-X Topology Layout Guidelines 8.6 41110 Layout Analysis 8.6.1 Embedded PCI-X 133 MHz 8.6.2 Embedded PCI-X 100 MHz Table 11. Embedded PCI-X 100 MHz Routing Recommendations 8.6.3 PCI-X 66 MHz Embedded Topology Table 12. PCI-X 66 MHz Embedded Routing Recommendations 8.6.4 PCI 66 MHz Embedded Topology Figure 20 and Tabl e 13 provide routing details for a topology with an embedded PCI 66MHz design. Figure 20. PCI 66 MHz Embedded Topology Table 13. PCI 66 MHz Embedded Table 8.6.5 PCI 33 MHz Embedded Mode Topology Table 14. PCI 33 MHz Embedded Routing Recommendations PCI Express Layout 9 9.1 General recommendations 9.2 PCI-Express Layout Guidelines 9.3 Adapter Card Layout Guidelines Page Page Circuit Implementations 10 10.1 41110 Analog Voltage Filters 10.1.1 PCI Analog Voltage Filters 10.1.2 PCI Express Analog Voltage Filter 10.1.3 Bandgap Analog Voltage Filter 10.2 41110 Reference and Compensation Pins 10.2.1 SM Bus Page 41110 Customer Reference Boards 11 11.1 Board Stack-up 11.2 Materi al 11.3 Impedance Page Page Design Guide Checklist 12 Table 20. PCI/PCI-X Interface S ignals (Sheet 1 of 2) Table 21. Miscellaneous Signals Table 20. PCI/PCI-X I nterface Signals (Sheet 2 of 2) Table 22. SMB us Interface Signals Table 21. Miscellaneous Signals Table 23. Reset Pins Table 24. Power and Ground Signals