IntelĀ® 41110 Serial to Parallel PCI Bridge Design Guide 17
Power Plane Layout 4
This chapter provides details on the decoupling and voltage planes needed to bias the 41110
package.

4.1 41110 Decoupling Guidelines

Tabl e 2 lists the decoupling guidelines for the 41110. Figure7 and Figure 8 provide the decoupling
capacitors around the 41110 ball grid pins.
Figure 7. Decoupling Placement for Core and PC I Express Voltage Planes
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