Intel 41110 manual Power Plane Layout, Decoupling Guidelines

Power Plane Layout 4

This chapter provides details on the decoupling and voltage planes needed to bias the 41110 package.

4.141110 Decoupling Guidelines

Table 2 lists the decoupling guidelines for the 41110. Figure 7 and Figure 8 provide the decoupling capacitors around the 41110 ball grid pins.

Figure 7. Decoupling Placement for Core and PCI Express Voltage Planes

B2713-01

Intel® 41110 Serial to Parallel PCI Bridge Design Guide 17