Reset and Power Timing Considerations5 | Intel 41110 instruction

41110 Reset and Power Timing

Considerations5

This chapter describes the 41110 reset timing considerations.

5.1A_RST# and PERST# Timing Requirements

The PCI-X Specification requires that there is a 100ms delay from valid power (PERST#) to reset deassertion (A_RST#). 41110 will keep A_RST# asserted for a minimum of 320ms after PERST# is deasserted.

5.2VCC15 and VCC33 Voltage Requirements

The following steps are the power sequencing requirements that must be followed with the 41110:

1.The 41110 requires that the VCC33 voltage rail be no less than 0.5V below VCC15 (absolute voltage value) at all times during 41110 operation, including during system power up and power down. In other words, the following must always be true:

VCC33 >= (VCC15 – 0.5V)

This can be accomplished by placing a diode (with a voltage drop <0.5V) between VCC15 and VCC33. A node will be connected to VCC15 and cathode will be connected to VCC33.

If VCC15 (1.5V PCI-X I/O voltage) and VCC15 (1.5V core voltage) are tied together on the platform, then both voltages must meet the above rule.

Note: Linear voltage regulators are recommended when using 1.5 Volt power supplies.

2.If a voltage regulator solution is used which shunts VCC15 to ground while VCC33 is powered, the maximum allowable time that VCC15 can be shunted to ground while VCC33 is fully powered is 20ms.

3.The maximum allowed time between VCC33 and VCC15 ramping is 525ms.

Note: There is no minimum sequencing time requirement other than requirements in Steps 2 and 3.

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Intel 41110 manual Reset and Power Timing Considerations5, ARST# and PERST# Timing Requirements

Contents

Design Guide Intel 41110 Serial to Parallel PCI Bridge Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables Figures Contents Date Revision Description March 001 Initial release Revision History Terminology and Definitions About This DocumentTerminology and Definitions Sheet 1 Term Definition Terminology and Definitions Sheet 2 About This Document PCI Express Interface Features PCI-X Interface FeaturesIntroduction2 SMBus for configuration register initialization Power ManagementSMBus Interface Introduction Microcontroller Connections to Microcontroller Block Diagram Related Documents Jtag Intel 41110 Serial to Parallel PCI Bridge Applications Block Diagram Adapter Card Block Diagram Package Information Package Specification Package Information Bridge Package Dimensions Side View 41110 Decoupling Guidelines Power Plane Layout Power Plane Layout Decoupling Guidelines Split Voltage Planes41110 300 PCI Reset and Power Timing Considerations5 ARST# and PERST# Timing RequirementsVCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations General Routing Guidelines General Routing GuidelinesCrosstalk General Routing Guidelines EMI Considerations Power Distribution and Decoupling Trace ImpedanceDecoupling Cross Section of Differential Trace Differential Impedance Board Layout Guidelines Adapter Card TopologyAdapter Card Stack Up, Microstrip and Stripline Adapter Card Stackup Board Layout Guidelines PCI-X Layout Guidelines AINT# Interrupt Pins PCI Express INTx MessageInterrupts INTx Routing Table Interrupt Routing for Devices Behind a Bridge PCI ArbitrationPCI-X Layout Guidelines Interrupt Binding for Devices Behind a Bridge PCI Resistor Compensation PCI General Layout Guidelines PCI Clock Layout Guidelines PCI-X SignalsPCI Pullup Resistors Not Required PCI/PCI-X Frequency/Mode Straps PCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary PCI-X Topology Layout Guidelines 41110 Layout AnalysisPCI-X Slot Guidelines Embedded PCI-X 133 MHz Embedded PCI-X 133 MHz Routing RecommendationsParameter Routing Guideline for Lower AD Bus Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHz PCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 66 MHz Embedded Topology PCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode Topology General recommendations PCI Express Layout Adapter Card Layout Guidelines PCI-Express Layout GuidelinesPCI Express Layout Adapter Card Routing Recommendations Sheet 1 Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations Config10.1 41110 Analog Voltage Filters Circuit Implementations PCI Express Analog Voltage Filter PCI Analog Voltage Filters PCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage Filter Bandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation Pins SMBUs Address Configuration SM BusBit Value This page intentionally left blank Customer Reference Boards Layer Type Thickness Copper WeightBoard Stack-up CRB Board Stackup Sheet 1 Impedance MaterialCustomer Reference Boards CRB Board Stackup Sheet 2 Mechanical Outline Board Outline This page intentionally left blank PCI Express Interface Signals Design Guide ChecklistSignals Recommendations Reason/Impact PERCOMP10 PCI/PCI-X Interface Signals Sheet 1 Design Guide Checklist Miscellaneous Signals PCI/PCI-X Interface Signals Sheet 2 Recommendations Reason/Impact SMBus Interface Signals Ballout Pin Name Usage Reset Pins Signal Recommendations Reason/Impact Power and Ground Signals Jtag Signals This page intentionally left blank