Circuit Implementations
Figure 25. Reference and Compensation Circuit Implementations
Serial to
Parallel PCI
Bridge
10.2.1SM Bus
The SMBus interface does not have configuration registers. The SMBus address is set by the states of pins SMBUS[5] and SMBUS [3:1] when PERST# is asserted as described in Table 17.
Table 17. SMBUs Address Configuration
Bit | Value |
|
|
7 | 1 |
|
|
6 | 1 |
|
|
5 | SMBUS[5] |
|
|
4 | 0 |
|
|
3 | SMBUS[3] |
|
|
2 | SMBUS[2] |
|
|
1 | SMBUS[1] |
|
|
Refer to Section 2.4 for details on how to use the SMBus to initialize 41110 registers with a microcontroller.
Intel® 41110 Serial to Parallel PCI Bridge Design Guide | 49 |
