Intel 41110 10.2.1 SM Bus

Intel® 41110 Serial to Parallel PCI Bridge Design Guide 49
Circuit Implementations
Figure 25. Reference and Compensation Circuit Implementations
10.2.1 SM Bus
The SMBus interface does not have configuration registers. The SMBus address is set by the states
of pins SMBUS[5] and SMBUS [3:1] when PERST# is asserted as described in Tabl e 17.
Refer to Section 2.4 for details on how to use the SMBus to initialize 41110 registers with a
microcontroller.
Serial to
Parallel PCI
Bridge
Table 17. SMBUs Address Configuration
Bit Value
71
61
5SMBUS[5]
40
3SMBUS[3]
2SMBUS[2]
1SMBUS[1]