PCI-X Layout Guidelines

8.6.2Embedded PCI-X 100 MHz

This section lists the embedded routing recommendations for PCI-X 100 MHz. Figure 18 shows the block diagram of this topology and Table 11 describes the routing recommendations.

Figure 18. Embedded PCI-X 100 MHz Topology

TL_EM1 EM1

TL1

TL_EM3 EM3

TL_EM2 EM2

B2720 -01

Table 11.

Embedded PCI-X 100 MHz Routing Recommendations

 

 

 

 

Parameter

Routing Guideline for Lower AD Bus

 

 

 

 

Reference Plane

Route over an unbroken ground plane

 

 

 

 

Board Impedance

60 +/- 15%

 

 

 

 

Stripline Trace Spacing

12 mils from edge to edge

 

 

 

 

Microstrip Trace Spacing

18 mils, from edge to edge

 

 

 

 

Break Out

5 mils on 5 mils spacing. Maximum length of breakout region can be 500 mils

 

 

 

 

Group Spacing

Spacing from other groups: 25 mils min, edge to edge

 

 

 

 

Trace Length 1 (TL1): From

 

 

41110 signal Ball to first

0.5” min - 3.0” max

 

junction

 

 

 

 

 

Trace Length: TL_EM1: from

 

 

41110 signal ball to the first

2.5” min - 3.5” max

 

embedded device

 

 

Trace Length TL_EM2 -

 

 

TL_EM3: from junction to the

1.5” min - 3.5” max

 

embedded device

 

 

 

 

 

Length Matching

Clocks coming form the clock driver must be on the same layer and length

 

Requirements:

matched to within 25 mils.

 

 

 

 

Number of vias

4 vias max per path

 

 

 

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Intel 41110 manual Embedded PCI-X 100 MHz Routing Recommendations