Microcontroller Connections to | Intel 41110 instruction

Introduction

Figure 1. Microcontroller Block Diagram

Serial to Parallel

PCI Bridge

2.4.2Microcontroller Connections to the 41110

Figure 2 shows the SMB interface from the 41110 to the microcontroller.

Intel® 41110 Serial to Parallel PCI Bridge Design Guide

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Intel 41110 manual Microcontroller Connections to, Microcontroller Block Diagram

Contents

Design Guide Intel 41110 Serial to Parallel PCI Bridge Intel 41110 Serial to Parallel PCI Bridge Design Guide Contents Tables Figures Contents Date Revision Description March 001 Initial release Revision History Term Definition About This DocumentTerminology and Definitions Terminology and Definitions Sheet 1 Terminology and Definitions Sheet 2 About This Document Introduction2 PCI Express Interface FeaturesPCI-X Interface Features Introduction Power ManagementSMBus for configuration register initialization SMBus Interface Microcontroller Connections to Microcontroller Block Diagram Related Documents Jtag Intel 41110 Serial to Parallel PCI Bridge Applications Block Diagram Adapter Card Block Diagram Package Information Package Specification Package Information Bridge Package Dimensions Side View 41110 Decoupling Guidelines Power Plane Layout Power Plane Layout 300 Split Voltage PlanesDecoupling Guidelines 41110 PCI VCC15 and VCC33 Voltage Requirements Reset and Power Timing Considerations5ARST# and PERST# Timing Requirements Reset and Power Timing Considerations Crosstalk General Routing GuidelinesGeneral Routing Guidelines General Routing Guidelines EMI Considerations Decoupling Power Distribution and DecouplingTrace Impedance Cross Section of Differential Trace Differential Impedance Adapter Card Stack Up, Microstrip and Stripline Board Layout GuidelinesAdapter Card Topology Adapter Card Stackup Board Layout Guidelines INTx Routing Table AINT# Interrupt Pins PCI Express INTx MessagePCI-X Layout Guidelines Interrupts Interrupt Binding for Devices Behind a Bridge PCI ArbitrationInterrupt Routing for Devices Behind a Bridge PCI-X Layout Guidelines PCI Resistor Compensation PCI General Layout Guidelines PCI/PCI-X Frequency/Mode Straps PCI-X SignalsPCI Clock Layout Guidelines PCI Pullup Resistors Not Required PCI Clock Distribution and Matching Requirements Parameter Routing Guidelines PCI-X Clock Layout Requirements Summary PCI-X Slot Guidelines PCI-X Topology Layout Guidelines41110 Layout Analysis Parameter Routing Guideline for Lower AD Bus Embedded PCI-X 133 MHzEmbedded PCI-X 133 MHz Routing Recommendations Embedded PCI-X 100 MHz Routing Recommendations Embedded PCI-X 100 MHz PCI-X 66 MHz Embedded Routing Recommendations PCI-X 66 MHz Embedded Topology PCI 66 MHz Embedded Table PCI 66 MHz Embedded Topology PCI 33 MHz Embedded Routing Recommendations PCI 33 MHz Embedded Mode Topology General recommendations PCI Express Layout Adapter Card Routing Recommendations Sheet 1 PCI-Express Layout GuidelinesAdapter Card Layout Guidelines PCI Express Layout Adapter Card Routing Recommendations Sheet 2 This page intentionally left blank Circuit Implementations ConfigCircuit Implementations 10.1 41110 Analog Voltage Filters PCI Express Analog Voltage Filter PCI Analog Voltage Filters PCI Express Analog Voltage Filter Circuit Bandgap Analog Voltage Filter Bandgap Analog Voltage Filter Circuit 10.2 41110 Reference and Compensation Pins Bit Value SMBUs Address ConfigurationSM Bus This page intentionally left blank CRB Board Stackup Sheet 1 Layer Type Thickness Copper WeightCustomer Reference Boards Board Stack-up CRB Board Stackup Sheet 2 MaterialImpedance Customer Reference Boards Mechanical Outline Board Outline This page intentionally left blank PERCOMP10 Design Guide ChecklistPCI Express Interface Signals Signals Recommendations Reason/Impact PCI/PCI-X Interface Signals Sheet 1 Design Guide Checklist Miscellaneous Signals PCI/PCI-X Interface Signals Sheet 2 Recommendations Reason/Impact SMBus Interface Signals Ballout Pin Name Usage Reset Pins Signal Recommendations Reason/Impact Power and Ground Signals Jtag Signals This page intentionally left blank